Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs

C. Weis, M. Jung, P. Ehses, C. Santos, P. Vivet, S.L.M. Goossens, M.L.P.J. Koedam, N. Wehn

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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Abstract

DRAM cells use capacitors as volatile and leaky bit storage elements. The time spent without refreshing them is called retention time. It is well known that the retention time depends inverse exponentially on the temperature. In 3D stacking, the challenges of high power densities and thermal dissipation are exacerbated and have a much stronger impact on the retention time of 3D-stacked WIDE I/O DRAMs that are placed on top of an MPSoC. Consequently, it is very important to study the temperature behaviour of WIDE I/O DRAMs. To the best of our knowledge, no investigations based on real measurements were done for stacked DRAM-on-logic devices. In this paper, we first provide detailed measurements on temperature-dependent retention time and bit error rates of WIDE I/O DRAMs. To obtain the correct temperature distribution of the WIDE-I/O DRAM die we use an advanced thermal modelling tool: the DOCEA AceThermalModeler™ (ATM). The WIDE I/O DRAM retention times and bit error rates are compared to the behaviour of 2D-DRAM chips (DIMMs) with the help of an advanced FPGA-based test system. We observed data pattern dependencies and variable retention times (VRTs). Second, based on this data, we develop and validate a SystemC-TLM2.0 DRAM bit error rate model. Our proposed DRAM bit error model enables early investigations on the temperature vs. retention time trade-off in future 3D-stacked MPSoCs with WIDE I/O DRAMs in SystemC-TLM2.0 environmen
Original languageEnglish
Title of host publicationDesign, Automation & Test in Europe Conference & Exhibition (DATE 2015, Grenoble, France, March 9-13, 2015)
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages495-500
ISBN (Print)978-3-9815-3704-8
Publication statusPublished - 2015

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    Weis, C., Jung, M., Ehses, P., Santos, C., Vivet, P., Goossens, S. L. M., Koedam, M. L. P. J., & Wehn, N. (2015). Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs. In Design, Automation & Test in Europe Conference & Exhibition (DATE 2015, Grenoble, France, March 9-13, 2015) (pp. 495-500). Institute of Electrical and Electronics Engineers.