Regular realization of symmetric functions using reversible logic

M.A. Perkowski, L. Jozwiak, P. Kerntopf, Andrzej Buller, M. Chrzanowska-Jeske, A. Mishchenko, Xiaoyu Song, A. Al-Rabadi, A. Coppola, B. Massey

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

38 Citations (Scopus)

Abstract

Reversible logic is of increasing importance to many future computer technologies. We introduce a regular structure to realize symmetric functions in binary reversible logic. This structure, called a 2*2 net structure, allows for a more efficient realization of symmetric functions than the methods introduced by the other authors. Our synthesis method allows us to realize arbitrary symmetric function in a completely regular structure of reversible gates with relatively little "garbage". Because every Boolean function can be made symmetric by repeating input variables, our method is applicable to arbitrary multi-input multi-output Boolean functions and realizes such arbitrary function in a circuit with a relatively small number of additional gate outputs. The method can also be used in classical logic. Its advantages in terms of numbers of gates and inputs/outputs are especially seen for symmetric or incompletely specified functions with many outputs.
Original languageEnglish
Title of host publicationProceedings DSD 2001 - Euromicro Symposium on Digital System Design, Warsaw, Poland, September 4-6, 2001
Place of PublicationLos Alamitos, CA, USA
PublisherIEEE Computer Society
Pages245-251
ISBN (Print)0-7695-1239-9
DOIs
Publication statusPublished - 2001
EventEuromicro Symposium on Digital System Design, 2001 - Warsaw, Poland
Duration: 4 Sep 20016 Sep 2001

Conference

ConferenceEuromicro Symposium on Digital System Design, 2001
Country/TerritoryPoland
CityWarsaw
Period4/09/016/09/01

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