Reduction of large resistor networks

J. Rommes, P.T.J. Lenaers, W.H.A. Schilders

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Abstract

Electro Static Discharge (ESD) analysis is of vital importance during the design of large-scale integrated circuits, since it gives insight in how well the interconnect can handle unintended peak charges. Due to the increasing amount of interconnect and metal layers, ESD analysis may become very time consuming or even unfeasible. We propose an algorithm for the reduction of large resistor networks, that typically arise during ESD, to much smaller equivalent networks. Experiments show reduction and speed-ups up to a factor 10.
Original languageEnglish
Title of host publicationScientific Computing in Electrical Engineering SCEE 2008
EditorsJ. Roos, L.R.J. Costa
Place of PublicationBerlin
PublisherSpringer
Pages555-562
ISBN (Print)978-3-642-12293-4
DOIs
Publication statusPublished - 2010

Publication series

NameMathematics in Industry
Volume14
ISSN (Print)1612-3956

Fingerprint

Dive into the research topics of 'Reduction of large resistor networks'. Together they form a unique fingerprint.

Cite this