Electro Static Discharge (ESD) analysis is of vital importance during the design of large-scale integrated circuits, since it gives insight in how well the interconnect can handle unintended peak charges. Due to the increasing amount of interconnect and metal layers, ESD analysis may become very time consuming or even unfeasible. We propose an algorithm for the reduction of large resistor networks, that typically arise during ESD, to much smaller equivalent networks. Experiments show reduction and speed-ups up to a factor 10.
|Title of host publication||Scientific Computing in Electrical Engineering SCEE 2008|
|Editors||J. Roos, L.R.J. Costa|
|Place of Publication||Berlin|
|Publication status||Published - 2010|
|Name||Mathematics in Industry|