Abstract
Cell-aware test (CAT) explicitly targets faults caused by defects inside library cells to improve test quality, compared with conventional automatic test pattern generation (ATPG) approaches, which target faults only at the boundaries of library cells. The CAT methodology consists of two stages. Stage 1, based on dedicated analog simulation, library characterization per cell identifies which cell-level test pattern detects which cell-internal defect; this detection information is encoded in a defect detection matrix (DDM). In Stage 2, with the DDMs as inputs, cell-aware ATPG generates chip-level test patterns per circuit design that is build up of interconnected instances of library cells. This paper focuses on Stage 1, library characterization, as both test quality and cost are determined by the set of cell-internal defects identified and simulated in the CAT tool flow. With the aim to achieve the best test quality, we first propose an approach to identify a comprehensive set, referred to as full set, of potential open- and short-defect locations based on cell layout. However, the full set of defects can be large even for a single cell, making the time cost of the defect simulation in Stage 1 unaffordable. Subsequently, to reduce the simulation time, we collapse the full set to a compact set of defects which serves as input of the defect simulation. The full set is stored for the diagnosis and failure analysis. With inspecting the simulation results, we propose a method to verify the test quality based on the compact set of defects and, if necessary, to compensate the test quality to the same level as that based on the full set of defects. For 351 combinational library cells in Cadence’s GPDK045 45nm library, we simulate only 5.4% defects from the full set to achieve the same test quality based on the full set of defects. In total, the simulation time, via linear extrapolation per cell, would be reduced by 96.4% compared with the time based on the full set of defects.
| Original language | English |
|---|---|
| Article number | https://doi.org/10.1007/s10836-021-05943-3 |
| Pages (from-to) | 161-189 |
| Number of pages | 29 |
| Journal | Journal of Electronic Testing : Theory and Applications |
| Volume | 37 |
| Issue number | 2 |
| DOIs | |
| Publication status | Published - 26 May 2021 |
Bibliographical note
Funding Information:We thank the following persons for their support. At Cadence Design Systems: Maxime Barbe, Vivek Chickermane, Franck Gerome, Walter Hartong, Anton Klotz, Robert McGowan, Michel Montanuy, Sylvie Parmantier, Mike Vachon, Carl Wisnesky, and Vladimir Zivkovic. At IMEC: Kristof Croes, Peter Debacker, Hilde De Witte, Ingrid De Wolf, Arul Mahesh Jagadeesa Das, Alessio Spessot, Ibrahim Tatar, and Diederik Verkest. At TU Delft: Said Hamdioui. At TU Eindhoven: Hailong Jiao. At National Tsing-Hua University: Min-Chun Hu and Cheng-Wen Wu. At University of Brussels: Dragomir Milojevic. Last but not least, we would thank the anonymous reviewer for his insightful question, which inspires us to improve our approach. Zhan Gao is financially supported by the China Scholarship Council (CSC) and Cadence Design Systems. Min-Chun Hu is financially supported by IMEC and National Tsing-Hua University.
Publisher Copyright:
© 2021, The Author(s).
Keywords
- Cell-aware test
- Defect location
- Equivalence
- Manufacturing defects
- Open defect
- Parasitic extraction
- Short defect
- Test quality compensation
- Verification