Recursive filtering on a vector DSP with linear speedup

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    Vector DSPs, or SIMD DSPs, have received considerable attention recently, since they are considered to be a viable alternative for dedicated hardware in signal processing for multimedia and wireless communication. It is possible to construct dedicated hardware for IIR filters with a linear speedup, but because of their recursive nature these filters are considered difficult to map efficiently on a vector DSP. The IIR programs for vector DSPs presented so far have their speedup bounded by the order of the filter. In this paper we present a program that has a linear speed up, in the sense that doubling the vector size doubles the throughput. The program is a vectorization of the incremental block-state architecture. The speedup of this program is not bounded by the order of the filter, and even works for low order filters. Besides strided memory access, no special processor features are required by our program. As a proof of concept we implemented it on the Philips EVP processor.
    Original languageEnglish
    Title of host publicationProceedings 16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2005)
    EditorsS. Vassiliadis
    Place of PublicationPiscataway
    PublisherInstitute of Electrical and Electronics Engineers
    Number of pages8
    ISBN (Print)0-7695-2407-9
    Publication statusPublished - 2005
    EventASAP 2005 - Samos, Greece
    Duration: 23 Jul 200525 Jul 2005


    ConferenceASAP 2005


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