Reconfigurable sigma delta ADC architecture for area efficient calibration

K.J. Pol, J.A. Hegt, S.F. Ouzounov, A.H.M. van Roermund

Research output: Contribution to conferencePoster

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CMOS technology has seen a trend of scaling. Digital and RF circuits benefit from this scaling as it results in reduced area and higher operating frequencies. Analog circuits, in many cases, suffer from this scaling. Designing precision analog circuits becomes increasingly difficult as CMOS technology scales. As a result, classically established design approaches do not work satisfactorily. Creative circuit design techniques have to be applied to build precision analog blocks. This time consuming process often results in the circuit being over-designed to meet process, voltage and temperature (PVT) corners. This wastes resources and, in many cases, results in sub-optimal performance. Calibration can increase the effective analog precision at the cost of slightly increased digital complexity. Calibration thus acts as a safety net for more ambitious designs while keeping the design time practical.
Calibration requires the designed circuit to incorporate some form of redundancy in its architecture. This redundancy depends on the quantity being calibrated. The cut-off frequency of a filter defined by its RC time constant may require tuning to compensate for the effects of component variation. This is accomplished by using extra resistors and/or capacitors and switching them in as required. This form of redundancy uses extra passive components. An amplifier whose gain is defined by its bias current may require redundancy in the form of extra current sources to tune away variations in the bias current.
Continuous time sigma delta modulators (CT-SDMs) have successfully met the industry demands for high resolution using relatively simple circuits. However, an upper bound on that resolution is imposed by various non-idealities that CT-SDMs suffer from. Calibrating CT-SDMs also requires redundancy in its structure. However, redundancy costs area and power. This work aims to investigate various system level and circuit level techniques of implementing redundancy while keeping the area and power tradeoff to a minimum.
In order to minimize the area cost for implementing redundancy, a new feedback DAC circuit is proposed. This new circuit implements a programmable gain using a programmable time reference. This programmability facilitates the use of the multiple feedback sigma delta modulator architecture. Using this structure the loop coefficients can be programmed by simply programming the time reference. This results in a compact architecture which is also power efficient.
Original languageEnglish
Publication statusPublished - 24 Mar 2015
EventICT.OPEN 2015 - De Flint , Amersfoort, Netherlands
Duration: 24 Mar 201525 Mar 2015


ConferenceICT.OPEN 2015
OtherThe Interface for Dutch ICT-Research
Internet address


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