Reconfigurable FPGA coprocessor for fast computations in multiple-valued logic

L. Jozwiak; M.A. Perkowski; D. Foote

Reconfigurable FPGA coprocessor for fast computations in multiple-valued logic

L. Jozwiak, M.A. Perkowski, D. Foote

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Original language	English
Title of host publication	Proc. IWLAS '97, International Workshop on Logic and Architecture Synthesis
Place of Publication	Grenoble, France
Publisher	Institute National Polytechnique de Grenoble
Pages	83-92
Publication status	Published - 1997
Event	conference; Proc. IWLAS '97, International Workshop on Logic and Architecture Synthesis, Grenoble, France, 16-18 December 1997 - Duration: 1 Jan 1997 → …

Conference

Conference	conference; Proc. IWLAS '97, International Workshop on Logic and Architecture Synthesis, Grenoble, France, 16-18 December 1997
Period	1/01/97 → …
Other	Proc. IWLAS '97, International Workshop on Logic and Architecture Synthesis, Grenoble, France, 16-18 December 1997

Cite this

@inproceedings{c50f6e77b0584adea33df5fa2cce8cbe,

title = "Reconfigurable FPGA coprocessor for fast computations in multiple-valued logic",

author = "L. Jozwiak and M.A. Perkowski and D. Foote",

year = "1997",

language = "English",

pages = "83--92",

booktitle = "Proc. IWLAS '97, International Workshop on Logic and Architecture Synthesis",

publisher = "Institute National Polytechnique de Grenoble",

note = "conference; Proc. IWLAS '97, International Workshop on Logic and Architecture Synthesis, Grenoble, France, 16-18 December 1997 ; Conference date: 01-01-1997",

}

Jozwiak, L, Perkowski, MA & Foote, D 1997, Reconfigurable FPGA coprocessor for fast computations in multiple-valued logic. in Proc. IWLAS '97, International Workshop on Logic and Architecture Synthesis. Institute National Polytechnique de Grenoble, Grenoble, France, pp. 83-92, conference; Proc. IWLAS '97, International Workshop on Logic and Architecture Synthesis, Grenoble, France, 16-18 December 1997, 1/01/97.

Reconfigurable FPGA coprocessor for fast computations in multiple-valued logic. / Jozwiak, L.; Perkowski, M.A.; Foote, D.
Proc. IWLAS '97, International Workshop on Logic and Architecture Synthesis. Grenoble, France: Institute National Polytechnique de Grenoble, 1997. p. 83-92.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Reconfigurable FPGA coprocessor for fast computations in multiple-valued logic

AU - Jozwiak, L.

AU - Perkowski, M.A.

AU - Foote, D.

PY - 1997

Y1 - 1997

M3 - Conference contribution

SP - 83

EP - 92

BT - Proc. IWLAS '97, International Workshop on Logic and Architecture Synthesis

PB - Institute National Polytechnique de Grenoble

CY - Grenoble, France

T2 - conference; Proc. IWLAS '97, International Workshop on Logic and Architecture Synthesis, Grenoble, France, 16-18 December 1997

Y2 - 1 January 1997

ER -