Realisation of a 0.25 μm NMOSFET using GexSi1-x (x≪0.4) as gate material

C. Salm, J. Schmitz, M.C. Martens, D. J. Gravesteijn, J. Holleman, P. H. Woerlee

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

1 Citation (Scopus)

Abstract

The realisation a 0.25 μm NMOSFET using arsenic implanted GexSi1-xas gate material, with minimal changes in an existing process is reported. The etching of this gate material does not pose a problem and the underlying thin gate oxide is hardly attacked. We will show good transistor characteristics for both a 6nm and a 4.5 nm oxide thickness. VTroll-off is comparable for the poly-Si and poly-GexSi1-xgates.

Original languageEnglish
Title of host publicationESSDERC 1996 - Proceedings of the 26th European Solid State Device Research Conference
EditorsMassimo Rudan, Giorgio Baccarani
PublisherIEEE Computer Society
Pages601-604
Number of pages4
ISBN (Print)9782863321966, 286332196X
Publication statusPublished - 1 Jan 1996
Externally publishedYes
Event26th European Solid State Device Research Conference, ESSDERC 1996 - Bologna, Italy
Duration: 9 Sep 199611 Sep 1996

Conference

Conference26th European Solid State Device Research Conference, ESSDERC 1996
Country/TerritoryItaly
CityBologna
Period9/09/9611/09/96

Fingerprint

Dive into the research topics of 'Realisation of a 0.25 μm NMOSFET using GexSi1-x (x≪0.4) as gate material'. Together they form a unique fingerprint.

Cite this