Abstract
Today’s embedded applications demand high compute performance at a tight energy budget, which requires a high compute efficiency. Compute efficiency is upper-bound by the technology node, however in practice programmable devices are orders of magnitude away from achieving this intrinsic compute efficiency. This work investigates the sources of inefficiency that cause this, and identifies four key design guidelines that can steer compute efficiency towards sub-picojoule per operation. Based on these guidelines a novel architecture with adaptive micro-architecture, and accompanying tool flow is proposed.
| Original language | English |
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| Pages | 1-7 |
| Number of pages | 7 |
| Publication status | Published - 18 Jan 2016 |
| Event | 9th International Workshop on Programmability and Architectures for Heterogeneous Multicores (MULTIPROG-2016), January 18, 2016, Prague, Czech Republic - Prague, Czech Republic Duration: 18 Jan 2016 → 18 Jan 2016 http://research.ac.upc.edu/multiprog/ |
Workshop
| Workshop | 9th International Workshop on Programmability and Architectures for Heterogeneous Multicores (MULTIPROG-2016), January 18, 2016, Prague, Czech Republic |
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| Abbreviated title | MULTIPROG-2016 |
| Country/Territory | Czech Republic |
| City | Prague |
| Period | 18/01/16 → 18/01/16 |
| Other | Workshop held in conjunction with the 11th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC 2016) |
| Internet address |
Keywords
- adaptive micro-architecture
- intrinsic compute efficiency
- spatial layout