Re-enactment simulation for buffer size optimization in semiconductor back-end production

Jelle Adan, Stephan Sneijders, Alp Akcay, Ivo J.B.F. Adan

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Abstract

In this work, we propose a re-enactment simulation-based optimization method to determine the minimal total buffer capacity in an assembly line required to meet a target throughput. A distinguishing feature is the use of real-time event traces, in a fast fluid flow simulation model. Employing real-time event traces avoids the necessity to make restrictive modeling assumptions. The fluid simulation is combined with a multi start search algorithm. To demonstrate its effectiveness, the method is applied to a real-world use case in lead frame based semiconductor back-end manufacturing. This use case considers an assembly line consisting of six machines, for which the proposed method determines optimal buffer size configurations within several minutes of computational time.

LanguageEnglish
Title of host publicationWSC 2018 - 2018 Winter Simulation Conference
Subtitle of host publicationSimulation for a Noble Cause
EditorsM. Rabe, A.A. Juan, N. Mustafee, A. Skoogh, S. Jain, B. Johansson
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages3432-3440
Number of pages9
ISBN (Electronic)9781538665725
DOIs
StatePublished - 31 Jan 2019
Event2018 Winter Simulation Conference, WSC 2018 - Gothenburg, Sweden
Duration: 9 Dec 201812 Dec 2018

Conference

Conference2018 Winter Simulation Conference, WSC 2018
Abbreviated titleWSC 2018
CountrySweden
CityGothenburg
Period9/12/1812/12/18

Fingerprint

Assembly Line
Use Case
Buffer
Semiconductors
Trace
Semiconductor materials
Simulation-based Optimization
Real-time
Multistart
Optimization
Flow simulation
Flow Simulation
Search Algorithm
Fluid Flow
Optimization Methods
Flow of fluids
Simulation
Simulation Model
Throughput
Lead

Cite this

Adan, J., Sneijders, S., Akcay, A., & Adan, I. J. B. F. (2019). Re-enactment simulation for buffer size optimization in semiconductor back-end production. In M. Rabe, A. A. Juan, N. Mustafee, A. Skoogh, S. Jain, & B. Johansson (Eds.), WSC 2018 - 2018 Winter Simulation Conference: Simulation for a Noble Cause (pp. 3432-3440). [8632251] Piscataway: Institute of Electrical and Electronics Engineers. DOI: 10.1109/WSC.2018.8632251
Adan, Jelle ; Sneijders, Stephan ; Akcay, Alp ; Adan, Ivo J.B.F./ Re-enactment simulation for buffer size optimization in semiconductor back-end production. WSC 2018 - 2018 Winter Simulation Conference: Simulation for a Noble Cause. editor / M. Rabe ; A.A. Juan ; N. Mustafee ; A. Skoogh ; S. Jain ; B. Johansson. Piscataway : Institute of Electrical and Electronics Engineers, 2019. pp. 3432-3440
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abstract = "In this work, we propose a re-enactment simulation-based optimization method to determine the minimal total buffer capacity in an assembly line required to meet a target throughput. A distinguishing feature is the use of real-time event traces, in a fast fluid flow simulation model. Employing real-time event traces avoids the necessity to make restrictive modeling assumptions. The fluid simulation is combined with a multi start search algorithm. To demonstrate its effectiveness, the method is applied to a real-world use case in lead frame based semiconductor back-end manufacturing. This use case considers an assembly line consisting of six machines, for which the proposed method determines optimal buffer size configurations within several minutes of computational time.",
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Adan, J, Sneijders, S, Akcay, A & Adan, IJBF 2019, Re-enactment simulation for buffer size optimization in semiconductor back-end production. in M Rabe, AA Juan, N Mustafee, A Skoogh, S Jain & B Johansson (eds), WSC 2018 - 2018 Winter Simulation Conference: Simulation for a Noble Cause., 8632251, Institute of Electrical and Electronics Engineers, Piscataway, pp. 3432-3440, 2018 Winter Simulation Conference, WSC 2018, Gothenburg, Sweden, 9/12/18. DOI: 10.1109/WSC.2018.8632251

Re-enactment simulation for buffer size optimization in semiconductor back-end production. / Adan, Jelle; Sneijders, Stephan; Akcay, Alp; Adan, Ivo J.B.F.

WSC 2018 - 2018 Winter Simulation Conference: Simulation for a Noble Cause. ed. / M. Rabe; A.A. Juan; N. Mustafee; A. Skoogh; S. Jain; B. Johansson. Piscataway : Institute of Electrical and Electronics Engineers, 2019. p. 3432-3440 8632251.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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Adan J, Sneijders S, Akcay A, Adan IJBF. Re-enactment simulation for buffer size optimization in semiconductor back-end production. In Rabe M, Juan AA, Mustafee N, Skoogh A, Jain S, Johansson B, editors, WSC 2018 - 2018 Winter Simulation Conference: Simulation for a Noble Cause. Piscataway: Institute of Electrical and Electronics Engineers. 2019. p. 3432-3440. 8632251. Available from, DOI: 10.1109/WSC.2018.8632251