Re-enactment simulation for buffer size optimization in semiconductor back-end production

Jelle Adan; Stephan Sneijders; Alp Akcay; Ivo J.B.F. Adan

doi:10.1109/WSC.2018.8632251

Re-enactment simulation for buffer size optimization in semiconductor back-end production

Jelle Adan, Stephan Sneijders, Alp Akcay, Ivo J.B.F. Adan

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

1 Citation (Scopus)

2 Downloads (Pure)

Abstract

In this work, we propose a re-enactment simulation-based optimization method to determine the minimal total buffer capacity in an assembly line required to meet a target throughput. A distinguishing feature is the use of real-time event traces, in a fast fluid flow simulation model. Employing real-time event traces avoids the necessity to make restrictive modeling assumptions. The fluid simulation is combined with a multi start search algorithm. To demonstrate its effectiveness, the method is applied to a real-world use case in lead frame based semiconductor back-end manufacturing. This use case considers an assembly line consisting of six machines, for which the proposed method determines optimal buffer size configurations within several minutes of computational time.

Original language	English
Title of host publication	WSC 2018 - 2018 Winter Simulation Conference
Subtitle of host publication	Simulation for a Noble Cause
Editors	M. Rabe, A.A. Juan, N. Mustafee, A. Skoogh, S. Jain, B. Johansson
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	3432-3440
Number of pages	9
ISBN (Electronic)	9781538665725
DOIs	https://doi.org/10.1109/WSC.2018.8632251
Publication status	Published - 31 Jan 2019
Event	2018 Winter Simulation Conference, WSC 2018 - Gothenburg, Sweden Duration: 9 Dec 2018 → 12 Dec 2018

Conference

Conference	2018 Winter Simulation Conference, WSC 2018
Abbreviated title	WSC 2018
Country/Territory	Sweden
City	Gothenburg
Period	9/12/18 → 12/12/18

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10.1109/WSC.2018.8632251

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Adan, J., Sneijders, S., Akcay, A., & Adan, I. J. B. F. (2019). Re-enactment simulation for buffer size optimization in semiconductor back-end production. In M. Rabe, A. A. Juan, N. Mustafee, A. Skoogh, S. Jain, & B. Johansson (Eds.), WSC 2018 - 2018 Winter Simulation Conference: Simulation for a Noble Cause (pp. 3432-3440). [8632251] Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/WSC.2018.8632251

Adan, Jelle ; Sneijders, Stephan ; Akcay, Alp et al. / Re-enactment simulation for buffer size optimization in semiconductor back-end production. WSC 2018 - 2018 Winter Simulation Conference: Simulation for a Noble Cause. editor / M. Rabe ; A.A. Juan ; N. Mustafee ; A. Skoogh ; S. Jain ; B. Johansson. Piscataway : Institute of Electrical and Electronics Engineers, 2019. pp. 3432-3440

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abstract = "In this work, we propose a re-enactment simulation-based optimization method to determine the minimal total buffer capacity in an assembly line required to meet a target throughput. A distinguishing feature is the use of real-time event traces, in a fast fluid flow simulation model. Employing real-time event traces avoids the necessity to make restrictive modeling assumptions. The fluid simulation is combined with a multi start search algorithm. To demonstrate its effectiveness, the method is applied to a real-world use case in lead frame based semiconductor back-end manufacturing. This use case considers an assembly line consisting of six machines, for which the proposed method determines optimal buffer size configurations within several minutes of computational time.",

author = "Jelle Adan and Stephan Sneijders and Alp Akcay and Adan, {Ivo J.B.F.}",

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booktitle = "WSC 2018 - 2018 Winter Simulation Conference",

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Adan, J, Sneijders, S, Akcay, A & Adan, IJBF 2019, Re-enactment simulation for buffer size optimization in semiconductor back-end production. in M Rabe, AA Juan, N Mustafee, A Skoogh, S Jain & B Johansson (eds), WSC 2018 - 2018 Winter Simulation Conference: Simulation for a Noble Cause., 8632251, Institute of Electrical and Electronics Engineers, Piscataway, pp. 3432-3440, 2018 Winter Simulation Conference, WSC 2018, Gothenburg, Sweden, 9/12/18. https://doi.org/10.1109/WSC.2018.8632251

Re-enactment simulation for buffer size optimization in semiconductor back-end production. / Adan, Jelle; Sneijders, Stephan; Akcay, Alp et al.

WSC 2018 - 2018 Winter Simulation Conference: Simulation for a Noble Cause. ed. / M. Rabe; A.A. Juan; N. Mustafee; A. Skoogh; S. Jain; B. Johansson. Piscataway : Institute of Electrical and Electronics Engineers, 2019. p. 3432-3440 8632251.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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PY - 2019/1/31

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N2 - In this work, we propose a re-enactment simulation-based optimization method to determine the minimal total buffer capacity in an assembly line required to meet a target throughput. A distinguishing feature is the use of real-time event traces, in a fast fluid flow simulation model. Employing real-time event traces avoids the necessity to make restrictive modeling assumptions. The fluid simulation is combined with a multi start search algorithm. To demonstrate its effectiveness, the method is applied to a real-world use case in lead frame based semiconductor back-end manufacturing. This use case considers an assembly line consisting of six machines, for which the proposed method determines optimal buffer size configurations within several minutes of computational time.

AB - In this work, we propose a re-enactment simulation-based optimization method to determine the minimal total buffer capacity in an assembly line required to meet a target throughput. A distinguishing feature is the use of real-time event traces, in a fast fluid flow simulation model. Employing real-time event traces avoids the necessity to make restrictive modeling assumptions. The fluid simulation is combined with a multi start search algorithm. To demonstrate its effectiveness, the method is applied to a real-world use case in lead frame based semiconductor back-end manufacturing. This use case considers an assembly line consisting of six machines, for which the proposed method determines optimal buffer size configurations within several minutes of computational time.

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BT - WSC 2018 - 2018 Winter Simulation Conference

A2 - Rabe, M.

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PB - Institute of Electrical and Electronics Engineers

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Adan J, Sneijders S, Akcay A , Adan IJBF. Re-enactment simulation for buffer size optimization in semiconductor back-end production. In Rabe M, Juan AA, Mustafee N, Skoogh A, Jain S, Johansson B, editors, WSC 2018 - 2018 Winter Simulation Conference: Simulation for a Noble Cause. Piscataway: Institute of Electrical and Electronics Engineers. 2019. p. 3432-3440. 8632251 doi: 10.1109/WSC.2018.8632251

Re-enactment simulation for buffer size optimization in semiconductor back-end production

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