Abstract
In this work, we propose a re-enactment simulation-based optimization method to determine the minimal total buffer capacity in an assembly line required to meet a target throughput. A distinguishing feature is the use of real-time event traces, in a fast fluid flow simulation model. Employing real-time event traces avoids the necessity to make restrictive modeling assumptions. The fluid simulation is combined with a multi start search algorithm. To demonstrate its effectiveness, the method is applied to a real-world use case in lead frame based semiconductor back-end manufacturing. This use case considers an assembly line consisting of six machines, for which the proposed method determines optimal buffer size configurations within several minutes of computational time.
| Language | English |
|---|---|
| Title of host publication | WSC 2018 - 2018 Winter Simulation Conference |
| Subtitle of host publication | Simulation for a Noble Cause |
| Editors | M. Rabe, A.A. Juan, N. Mustafee, A. Skoogh, S. Jain, B. Johansson |
| Place of Publication | Piscataway |
| Publisher | Institute of Electrical and Electronics Engineers |
| Pages | 3432-3440 |
| Number of pages | 9 |
| ISBN (Electronic) | 9781538665725 |
| DOIs | |
| State | Published - 31 Jan 2019 |
| Event | 2018 Winter Simulation Conference, WSC 2018 - Gothenburg, Sweden Duration: 9 Dec 2018 → 12 Dec 2018 |
Conference
| Conference | 2018 Winter Simulation Conference, WSC 2018 |
|---|---|
| Abbreviated title | WSC 2018 |
| Country | Sweden |
| City | Gothenburg |
| Period | 9/12/18 → 12/12/18 |
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Re-enactment simulation for buffer size optimization in semiconductor back-end production. / Adan, Jelle; Sneijders, Stephan; Akcay, Alp; Adan, Ivo J.B.F.
WSC 2018 - 2018 Winter Simulation Conference: Simulation for a Noble Cause. ed. / M. Rabe; A.A. Juan; N. Mustafee; A. Skoogh; S. Jain; B. Johansson. Piscataway : Institute of Electrical and Electronics Engineers, 2019. p. 3432-3440 8632251.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
TY - GEN
T1 - Re-enactment simulation for buffer size optimization in semiconductor back-end production
AU - Adan,Jelle
AU - Sneijders,Stephan
AU - Akcay,Alp
AU - Adan,Ivo J.B.F.
PY - 2019/1/31
Y1 - 2019/1/31
N2 - In this work, we propose a re-enactment simulation-based optimization method to determine the minimal total buffer capacity in an assembly line required to meet a target throughput. A distinguishing feature is the use of real-time event traces, in a fast fluid flow simulation model. Employing real-time event traces avoids the necessity to make restrictive modeling assumptions. The fluid simulation is combined with a multi start search algorithm. To demonstrate its effectiveness, the method is applied to a real-world use case in lead frame based semiconductor back-end manufacturing. This use case considers an assembly line consisting of six machines, for which the proposed method determines optimal buffer size configurations within several minutes of computational time.
AB - In this work, we propose a re-enactment simulation-based optimization method to determine the minimal total buffer capacity in an assembly line required to meet a target throughput. A distinguishing feature is the use of real-time event traces, in a fast fluid flow simulation model. Employing real-time event traces avoids the necessity to make restrictive modeling assumptions. The fluid simulation is combined with a multi start search algorithm. To demonstrate its effectiveness, the method is applied to a real-world use case in lead frame based semiconductor back-end manufacturing. This use case considers an assembly line consisting of six machines, for which the proposed method determines optimal buffer size configurations within several minutes of computational time.
UR - http://www.scopus.com/inward/record.url?scp=85062595310&partnerID=8YFLogxK
U2 - 10.1109/WSC.2018.8632251
DO - 10.1109/WSC.2018.8632251
M3 - Conference contribution
SP - 3432
EP - 3440
BT - WSC 2018 - 2018 Winter Simulation Conference
PB - Institute of Electrical and Electronics Engineers
CY - Piscataway
ER -