Re-enactment simulation for buffer size optimization in semiconductor back-end production

Jelle Adan, Stephan Sneijders, Alp Akcay, Ivo J.B.F. Adan

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

1 Citation (Scopus)
2 Downloads (Pure)

Abstract

In this work, we propose a re-enactment simulation-based optimization method to determine the minimal total buffer capacity in an assembly line required to meet a target throughput. A distinguishing feature is the use of real-time event traces, in a fast fluid flow simulation model. Employing real-time event traces avoids the necessity to make restrictive modeling assumptions. The fluid simulation is combined with a multi start search algorithm. To demonstrate its effectiveness, the method is applied to a real-world use case in lead frame based semiconductor back-end manufacturing. This use case considers an assembly line consisting of six machines, for which the proposed method determines optimal buffer size configurations within several minutes of computational time.

Original languageEnglish
Title of host publicationWSC 2018 - 2018 Winter Simulation Conference
Subtitle of host publicationSimulation for a Noble Cause
EditorsM. Rabe, A.A. Juan, N. Mustafee, A. Skoogh, S. Jain, B. Johansson
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages3432-3440
Number of pages9
ISBN (Electronic)9781538665725
DOIs
Publication statusPublished - 31 Jan 2019
Event2018 Winter Simulation Conference, WSC 2018 - Gothenburg, Sweden
Duration: 9 Dec 201812 Dec 2018

Conference

Conference2018 Winter Simulation Conference, WSC 2018
Abbreviated titleWSC 2018
CountrySweden
CityGothenburg
Period9/12/1812/12/18

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