Re-addressing SRAM design and measurement for sub-threshold operation in view of classic 6T vs. standard cell based implementations

Xin Fan; Jan Stuijt; Rui Wang; Bo Liu; Tobias Gemmeke

doi:10.1109/ISQED.2017.7918294

Re-addressing SRAM design and measurement for sub-threshold operation in view of classic 6T vs. standard cell based implementations

Xin Fan, Jan Stuijt, Rui Wang, Bo Liu, Tobias Gemmeke

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

4 Citations (Scopus)

Abstract

This paper re-addresses standard-cell based SRAM design for sub-threshold operation. Rather than using flip-flop or latch gates to implement SRAM bitcells, a circuit structure that is fully based on combinational logic, OAI (Or-And-Invert) and AOI (And-Or-Invert) gates, is presented. Measurements on a 90-kb 40-nm SRAM chip show that, the OAI/AOI-based SRAM operates at a minimum access voltage of 410 mV and obtains a minimum read energy of 30 fJ per access per bit. At the data retention voltage of 330 mV, it features a leakage power of 1.6 pW per bit. Taking the proposed SRAM and a classic 6T-cell design as examples, the relationship between yield and bias in key figures of merit of a SRAM is highlighted based on silicon measurement results. This motivates a statistical view on the evaluation of SRAMs operating in sub-threshold.

Original language	English
Title of host publication	Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017 : March 14-15, 2017, Santa Clara, California USA
Place of Publication	Piscataway
Publisher	IEEE Computer Society
Pages	65-70
Number of pages	6
ISBN (Electronic)	978-1-5090-5404-6
ISBN (Print)	978-1-5090-5405-3
DOIs	https://doi.org/10.1109/ISQED.2017.7918294
Publication status	Published - 2 May 2017
Externally published	Yes
Event	18th International Symposium on Quality Electronic Design, ISQED 2017 - Santa Clara, United States Duration: 14 Mar 2017 → 15 Mar 2017

Conference

Conference	18th International Symposium on Quality Electronic Design, ISQED 2017
Country/Territory	United States
City	Santa Clara
Period	14/03/17 → 15/03/17

Keywords

leakage power
SRAM
standard cells
sub-threshold

Access to Document

10.1109/ISQED.2017.7918294

Cite this

Fan, X., Stuijt, J., Wang, R., Liu, B., & Gemmeke, T. (2017). Re-addressing SRAM design and measurement for sub-threshold operation in view of classic 6T vs. standard cell based implementations. In Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017 : March 14-15, 2017, Santa Clara, California USA (pp. 65-70). Article 7918294 IEEE Computer Society. https://doi.org/10.1109/ISQED.2017.7918294

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abstract = "This paper re-addresses standard-cell based SRAM design for sub-threshold operation. Rather than using flip-flop or latch gates to implement SRAM bitcells, a circuit structure that is fully based on combinational logic, OAI (Or-And-Invert) and AOI (And-Or-Invert) gates, is presented. Measurements on a 90-kb 40-nm SRAM chip show that, the OAI/AOI-based SRAM operates at a minimum access voltage of 410 mV and obtains a minimum read energy of 30 fJ per access per bit. At the data retention voltage of 330 mV, it features a leakage power of 1.6 pW per bit. Taking the proposed SRAM and a classic 6T-cell design as examples, the relationship between yield and bias in key figures of merit of a SRAM is highlighted based on silicon measurement results. This motivates a statistical view on the evaluation of SRAMs operating in sub-threshold.",

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author = "Xin Fan and Jan Stuijt and Rui Wang and Bo Liu and Tobias Gemmeke",

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Fan, X, Stuijt, J, Wang, R, Liu, B & Gemmeke, T 2017, Re-addressing SRAM design and measurement for sub-threshold operation in view of classic 6T vs. standard cell based implementations. in Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017 : March 14-15, 2017, Santa Clara, California USA., 7918294, IEEE Computer Society, Piscataway, pp. 65-70, 18th International Symposium on Quality Electronic Design, ISQED 2017, Santa Clara, California, United States, 14/03/17. https://doi.org/10.1109/ISQED.2017.7918294

Re-addressing SRAM design and measurement for sub-threshold operation in view of classic 6T vs. standard cell based implementations. / Fan, Xin; Stuijt, Jan; Wang, Rui et al.
Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017 : March 14-15, 2017, Santa Clara, California USA. Piscataway: IEEE Computer Society, 2017. p. 65-70 7918294.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AU - Liu, Bo

AU - Gemmeke, Tobias

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N2 - This paper re-addresses standard-cell based SRAM design for sub-threshold operation. Rather than using flip-flop or latch gates to implement SRAM bitcells, a circuit structure that is fully based on combinational logic, OAI (Or-And-Invert) and AOI (And-Or-Invert) gates, is presented. Measurements on a 90-kb 40-nm SRAM chip show that, the OAI/AOI-based SRAM operates at a minimum access voltage of 410 mV and obtains a minimum read energy of 30 fJ per access per bit. At the data retention voltage of 330 mV, it features a leakage power of 1.6 pW per bit. Taking the proposed SRAM and a classic 6T-cell design as examples, the relationship between yield and bias in key figures of merit of a SRAM is highlighted based on silicon measurement results. This motivates a statistical view on the evaluation of SRAMs operating in sub-threshold.

AB - This paper re-addresses standard-cell based SRAM design for sub-threshold operation. Rather than using flip-flop or latch gates to implement SRAM bitcells, a circuit structure that is fully based on combinational logic, OAI (Or-And-Invert) and AOI (And-Or-Invert) gates, is presented. Measurements on a 90-kb 40-nm SRAM chip show that, the OAI/AOI-based SRAM operates at a minimum access voltage of 410 mV and obtains a minimum read energy of 30 fJ per access per bit. At the data retention voltage of 330 mV, it features a leakage power of 1.6 pW per bit. Taking the proposed SRAM and a classic 6T-cell design as examples, the relationship between yield and bias in key figures of merit of a SRAM is highlighted based on silicon measurement results. This motivates a statistical view on the evaluation of SRAMs operating in sub-threshold.

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Fan X, Stuijt J, Wang R, Liu B, Gemmeke T. Re-addressing SRAM design and measurement for sub-threshold operation in view of classic 6T vs. standard cell based implementations. In Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017 : March 14-15, 2017, Santa Clara, California USA. Piscataway: IEEE Computer Society. 2017. p. 65-70. 7918294 doi: 10.1109/ISQED.2017.7918294

Re-addressing SRAM design and measurement for sub-threshold operation in view of classic 6T vs. standard cell based implementations

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Keywords

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