Re-addressing SRAM design and measurement for sub-threshold operation in view of classic 6T vs. standard cell based implementations

Xin Fan, Jan Stuijt, Rui Wang, Bo Liu, Tobias Gemmeke

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

1 Citation (Scopus)

Abstract

This paper re-addresses standard-cell based SRAM design for sub-threshold operation. Rather than using flip-flop or latch gates to implement SRAM bitcells, a circuit structure that is fully based on combinational logic, OAI (Or-And-Invert) and AOI (And-Or-Invert) gates, is presented. Measurements on a 90-kb 40-nm SRAM chip show that, the OAI/AOI-based SRAM operates at a minimum access voltage of 410 mV and obtains a minimum read energy of 30 fJ per access per bit. At the data retention voltage of 330 mV, it features a leakage power of 1.6 pW per bit. Taking the proposed SRAM and a classic 6T-cell design as examples, the relationship between yield and bias in key figures of merit of a SRAM is highlighted based on silicon measurement results. This motivates a statistical view on the evaluation of SRAMs operating in sub-threshold.

Original languageEnglish
Title of host publicationProceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017 : March 14-15, 2017, Santa Clara, California USA
Place of PublicationPiscataway
PublisherIEEE Computer Society
Pages65-70
Number of pages6
ISBN (Electronic)978-1-5090-5404-6
ISBN (Print)978-1-5090-5405-3
DOIs
Publication statusPublished - 2 May 2017
Externally publishedYes
Event18th International Symposium on Quality Electronic Design, ISQED 2017 - Santa Clara, United States
Duration: 14 Mar 201715 Mar 2017

Conference

Conference18th International Symposium on Quality Electronic Design, ISQED 2017
CountryUnited States
CitySanta Clara
Period14/03/1715/03/17

Keywords

  • leakage power
  • SRAM
  • standard cells
  • sub-threshold

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