Abstract
This paper addresses the crucial problem of static power reduction for circuits implemented in nano-CMOS technologies. Its solution requires accurate and rapid power estimation, but the known power simulators are not accurate and quick at the same time. The paper proposes and discusses a new rapid and very accurate leakage power estimation method and related simulator. The maximum estimation error of the simulator is within 5%, with an average error of only 0.57%, and run-times in the range of seconds, while for the same circuits HSPICE runs for hours or days.
Original language | English |
---|---|
Title of host publication | Proceedings of the 14th Euromicro Conference on Digital System Design (DSD'2011), August 31 - September 2, 2011, Oulu, Finland |
Editors | P. Kitsos |
Place of Publication | Piscataway |
Publisher | IEEE Computer Society |
Pages | 685-692 |
ISBN (Print) | 978-1-4577-1048-3 |
DOIs | |
Publication status | Published - 2011 |
Event | 14th Euromicro Conference on Digital System Design (DSD 2011) - Oulu, Finland Duration: 31 Aug 2011 → 2 Sep 2011 Conference number: 14 http://dsmc2.eap.gr/dsd2011/ |
Conference
Conference | 14th Euromicro Conference on Digital System Design (DSD 2011) |
---|---|
Abbreviated title | DSD 2011 |
Country/Territory | Finland |
City | Oulu |
Period | 31/08/11 → 2/09/11 |
Other | "Architectures, Methods and Tools" |
Internet address |