Rapid and accurate leakage power estimation for nano-CMOS circuits

M. Bryk, L. Jozwiak, W. Kuzmicz

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Abstract

This paper addresses the crucial problem of static power reduction for circuits implemented in nano-CMOS technologies. Its solution requires accurate and rapid power estimation, but the known power simulators are not accurate and quick at the same time. The paper proposes and discusses a new rapid and very accurate leakage power estimation method and related simulator. The maximum estimation error of the simulator is within 5%, with an average error of only 0.57%, and run-times in the range of seconds, while for the same circuits HSPICE runs for hours or days.
Original languageEnglish
Title of host publicationProceedings of the 14th Euromicro Conference on Digital System Design (DSD'2011), August 31 - September 2, 2011, Oulu, Finland
EditorsP. Kitsos
Place of PublicationPiscataway
PublisherIEEE Computer Society
Pages685-692
ISBN (Print)978-1-4577-1048-3
DOIs
Publication statusPublished - 2011
Event14th Euromicro Conference on Digital System Design (DSD 2011) - Oulu, Finland
Duration: 31 Aug 20112 Sep 2011
Conference number: 14
http://dsmc2.eap.gr/dsd2011/

Conference

Conference14th Euromicro Conference on Digital System Design (DSD 2011)
Abbreviated titleDSD 2011
CountryFinland
CityOulu
Period31/08/112/09/11
Other"Architectures, Methods and Tools"
Internet address

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