Rapid and accurate leakage power estimation for nano-CMOS circuits

M. Bryk; L. Jozwiak; W. Kuzmicz

doi:10.1109/DSD.2011.92

Rapid and accurate leakage power estimation for nano-CMOS circuits

M. Bryk, L. Jozwiak, W. Kuzmicz

Electronic Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Abstract

This paper addresses the crucial problem of static power reduction for circuits implemented in nano-CMOS technologies. Its solution requires accurate and rapid power estimation, but the known power simulators are not accurate and quick at the same time. The paper proposes and discusses a new rapid and very accurate leakage power estimation method and related simulator. The maximum estimation error of the simulator is within 5%, with an average error of only 0.57%, and run-times in the range of seconds, while for the same circuits HSPICE runs for hours or days.

Original language	English
Title of host publication	Proceedings of the 14th Euromicro Conference on Digital System Design (DSD'2011), August 31 - September 2, 2011, Oulu, Finland
Editors	P. Kitsos
Place of Publication	Piscataway
Publisher	IEEE Computer Society
Pages	685-692
ISBN (Print)	978-1-4577-1048-3
DOIs	https://doi.org/10.1109/DSD.2011.92
Publication status	Published - 2011
Event	14th Euromicro Conference on Digital System Design (DSD 2011) - Oulu, Finland Duration: 31 Aug 2011 → 2 Sep 2011 Conference number: 14 http://dsmc2.eap.gr/dsd2011/

Conference

Conference	14th Euromicro Conference on Digital System Design (DSD 2011)
Abbreviated title	DSD 2011
Country	Finland
City	Oulu
Period	31/08/11 → 2/09/11
Other	"Architectures, Methods and Tools"
Internet address	http://dsmc2.eap.gr/dsd2011/

Access to Document

10.1109/DSD.2011.92

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@inproceedings{024db89223d4494b8e95c564afd7b083,

title = "Rapid and accurate leakage power estimation for nano-CMOS circuits",

abstract = "This paper addresses the crucial problem of static power reduction for circuits implemented in nano-CMOS technologies. Its solution requires accurate and rapid power estimation, but the known power simulators are not accurate and quick at the same time. The paper proposes and discusses a new rapid and very accurate leakage power estimation method and related simulator. The maximum estimation error of the simulator is within 5%, with an average error of only 0.57%, and run-times in the range of seconds, while for the same circuits HSPICE runs for hours or days.",

author = "M. Bryk and L. Jozwiak and W. Kuzmicz",

year = "2011",

doi = "10.1109/DSD.2011.92",

language = "English",

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editor = "P. Kitsos",

booktitle = "Proceedings of the 14th Euromicro Conference on Digital System Design (DSD'2011), August 31 - September 2, 2011, Oulu, Finland",

publisher = "IEEE Computer Society",

address = "United States",

note = "14th Euromicro Conference on Digital System Design (DSD 2011), DSD 2011 ; Conference date: 31-08-2011 Through 02-09-2011",

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Bryk, M, Jozwiak, L & Kuzmicz, W 2011, Rapid and accurate leakage power estimation for nano-CMOS circuits. in P Kitsos (ed.), Proceedings of the 14th Euromicro Conference on Digital System Design (DSD'2011), August 31 - September 2, 2011, Oulu, Finland. IEEE Computer Society, Piscataway, pp. 685-692, 14th Euromicro Conference on Digital System Design (DSD 2011), Oulu, Finland, 31/08/11. https://doi.org/10.1109/DSD.2011.92

Rapid and accurate leakage power estimation for nano-CMOS circuits. / Bryk, M.; Jozwiak, L.; Kuzmicz, W.

Proceedings of the 14th Euromicro Conference on Digital System Design (DSD'2011), August 31 - September 2, 2011, Oulu, Finland. ed. / P. Kitsos. Piscataway : IEEE Computer Society, 2011. p. 685-692.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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N2 - This paper addresses the crucial problem of static power reduction for circuits implemented in nano-CMOS technologies. Its solution requires accurate and rapid power estimation, but the known power simulators are not accurate and quick at the same time. The paper proposes and discusses a new rapid and very accurate leakage power estimation method and related simulator. The maximum estimation error of the simulator is within 5%, with an average error of only 0.57%, and run-times in the range of seconds, while for the same circuits HSPICE runs for hours or days.

AB - This paper addresses the crucial problem of static power reduction for circuits implemented in nano-CMOS technologies. Its solution requires accurate and rapid power estimation, but the known power simulators are not accurate and quick at the same time. The paper proposes and discusses a new rapid and very accurate leakage power estimation method and related simulator. The maximum estimation error of the simulator is within 5%, with an average error of only 0.57%, and run-times in the range of seconds, while for the same circuits HSPICE runs for hours or days.

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DO - 10.1109/DSD.2011.92

M3 - Conference contribution

SN - 978-1-4577-1048-3

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BT - Proceedings of the 14th Euromicro Conference on Digital System Design (DSD'2011), August 31 - September 2, 2011, Oulu, Finland

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