Many modern applications in important application domains, as communication, image and video processing, multimedia, etc. involve much data-level parallelism (DLP). Therefore, adequate exploitation of DLP is highly relevant. This paper focuses on effective and efficient exploitation of DLP for the synthesis of vector VLIW ASIP processors. We propose analytical energy models in order to rapidly estimate the energy consumption of a nested loop executed on a VLIW ASIP with respect to different vector widths. The models perform a rapid and relatively accurate energy consumption estimation through combining the relevant information on the application and implementation technology. The analytical energy models are experimentally validated and the validation results are discussed.
|Title of host publication||Proceedings - 2013 2nd Mediterranean Conference on Embedded Computing, MECO 2013|
|Number of pages||5|
|Publication status||Published - 1 Dec 2013|
|Event||2013 2nd Mediterranean Conference on Embedded Computing, MECO 2013 - Budva, Montenegro|
Duration: 15 Jun 2013 → 20 Jun 2013
|Conference||2013 2nd Mediterranean Conference on Embedded Computing, MECO 2013|
|Period||15/06/13 → 20/06/13|