Platform-based Field Programmable Gate Arrays (FPGAs) have gained popularity for implementing multiprocessor system on chips (MPSoCs). The applications in an MPSoC can have high complexities and stringent Quality-of-Service (QoS) demands. Consequently, the problem of binding an application on an FPGA has become more challenging. An application requires logic and communication resources for computing and transporting data among its IPs. This in turn divides an FPGA into two virtual planes, i.e., logic and communication. Therefore, the available resources in both the FPGA planes should be taken into account by an application binding solution. Our proposed scheme performs placement unification with mapping and allocation (PUMA). This means PUMA accounts for the required (application) to the available (FPGA) resources in both the logic plane and the communication plane, simultaneously. A hardwired Network on Chip (HWNoC) serves as the communication plane for our FPGA, because of its scalable and isolated nature. Moreover, PUMA ensures that a successful binding solution fulfills an application QoS constraints. PUMA is implemented by using cycle-accurate transaction-level SystemC. PUMA performance and scalability is evaluated by using a number of synthetic applications. The PUMA application binding success rate exists in between 35% and 90%. Additionally, the cost of PUMA is evaluated against a real-world H.264 encoder.
|Title of host publication||Proceedings of the 14th Euromicro Conference on Digital System Design (DSD 2011), 31 August - 2 September 2011, Oulu, Finland|
|Place of Publication||Piscataway|
|Publisher||Institute of Electrical and Electronics Engineers|
|Publication status||Published - 2011|
Wahlah, M. A., & Goossens, K. G. W. (2011). PUMA: placement unification with mapping and guaranteed throughput allocation on FPGA using a hardwired NoC. In Proceedings of the 14th Euromicro Conference on Digital System Design (DSD 2011), 31 August - 2 September 2011, Oulu, Finland (pp. 88-96). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/DSD.2011.16