Nowadays in ASML more and more software components are created using formal methods. Although these components can be verified formally against certain properties, their validation still has to be done to ensure that the requirements are met. Validation via testing requires effort and increases lead-time in the software development process. This report describes an investigation on the possibilities of testing formal components. The use of protocol simulators is successfully proposed as a solution direction for the validation of such components.
|Award date||28 Sep 2017|
|Place of Publication||Eindhoven|
|Publication status||Published - 28 Sep 2017|