In this line of work, we study the Programmable / Re- con¯gurable (P/R) (i.e. Flexible) capabilities of Folding & Interpolating (F&I) ADC architecture. We present possible ways to introduce °exibility and trade accuracy for speed, using the Folding Factor (FF ), Number of Folding Blocks (NFB), Interpolation Factor (FINT ) and depth of cascading. We develop a SIMULINK model, which includes the main error mechanisms occurring in this ADC architecture and explore the trade-o®s between the above entioned quantities (FF ,NFB, FINT ) in relation to these main error mechanisms. The objective of the study is to propose optimum combinations of them as a function of total ADC resolution and speed and, ¯nally, to present circuit solutions that implement the aforementioned °exible options and comment on the non-idealities they might introduce. In this paper, as a ¯rst step for this study, we investigate three di®erent F&I ADC con¯gurations with the same resolution, but di®erent FF ,NFB, FINT , present the simulation results and draw conclusions.
|Title of host publication||Proceedings of ProRISC 2009, 20th Annual Workshop on Circuits Systems and Signal Processing, November 26-27, 2009, Veldhoven, The Netherlands|
|Place of Publication||Utrecht|
|Publisher||STW Technology Foundation|
|Publication status||Published - 2009|