SystemC is an IEEE standard system-level language used in hardware/software co-design and has been widely adopted in the industry. This paper describes a formal approach to verifying SystemC codes by providing a mapping to the process algebra mCRL2. The outstanding advantages of mCRL2 are the support for different data types and a powerful tool-set for model reduction and analysis. A tool is implemented to automatically perform the proposed mapping. This translation enabled us to exploit processalgebraic verification techniques to analyze a number of case-studies, including the formal analysis of a single-cycle and a pipelined MIPS processor specified in SystemC.
|Title of host publication||Proceedings 8th International Conference on Application of Concurrency to System Design (ACSD'08, Xian, China, June 23-27, 2008)|
|Publisher||Institute of Electrical and Electronics Engineers|
|Publication status||Published - 2008|