Predictive timing error calibration technique for RF current-streering DACs

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Abstract

Timing errors become more dominant in dynamic performance in high-resolution Radio Frequency DACs. It consumes a lot of power and area to reduce timing errors below picoseconds. To relax the requirements on circuit design and layout complexity, a predictive timing error calibration technique based on on-chip timing error measurement is demonstrated in this work. Matlab behavior level simulation shows that this on-chip calibration technique can improve the SFDR significantly in a 2GS/s DAC. Simulation results of a phase detector, the key circuit in this calibration technique, are given. The circuit is designed in a CMOS 90nm process.
Original languageEnglish
Title of host publicationProceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2008) 18 - 21 May 2008, Seattle, Washington, USA
Place of PublicationPiscataway, New Jersy, USA
PublisherInstitute of Electrical and Electronics Engineers
Pages228-231
ISBN (Print)978-1-424-41683-7
Publication statusPublished - 2008
Event2008 IEEE International Symposium on Circuits and Systems (ISCAS 2008) - Seattle, United States
Duration: 18 May 200821 May 2008

Conference

Conference2008 IEEE International Symposium on Circuits and Systems (ISCAS 2008)
Abbreviated titleISCAS 2008
CountryUnited States
CitySeattle
Period18/05/0821/05/08

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    Tang, Y., Hegt, J. A., & Roermund, van, A. H. M. (2008). Predictive timing error calibration technique for RF current-streering DACs. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2008) 18 - 21 May 2008, Seattle, Washington, USA (pp. 228-231). Institute of Electrical and Electronics Engineers.