Predictive timing error calibration technique for RF current-streering DACs

Y. Tang; J.A. Hegt; A.H.M. Roermund, van

Predictive timing error calibration technique for RF current-streering DACs

Y. Tang, J.A. Hegt, A.H.M. Roermund, van

Integrated Circuits

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Abstract

Timing errors become more dominant in dynamic performance in high-resolution Radio Frequency DACs. It consumes a lot of power and area to reduce timing errors below picoseconds. To relax the requirements on circuit design and layout complexity, a predictive timing error calibration technique based on on-chip timing error measurement is demonstrated in this work. Matlab behavior level simulation shows that this on-chip calibration technique can improve the SFDR significantly in a 2GS/s DAC. Simulation results of a phase detector, the key circuit in this calibration technique, are given. The circuit is designed in a CMOS 90nm process.

Original language	English
Title of host publication	Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2008) 18 - 21 May 2008, Seattle, Washington, USA
Place of Publication	Piscataway, New Jersy, USA
Publisher	Institute of Electrical and Electronics Engineers
Pages	228-231
ISBN (Print)	978-1-424-41683-7
Publication status	Published - 2008
Event	2008 IEEE International Symposium on Circuits and Systems (ISCAS 2008) - Seattle, United States Duration: 18 May 2008 → 21 May 2008

Conference

Conference	2008 IEEE International Symposium on Circuits and Systems (ISCAS 2008)
Abbreviated title	ISCAS 2008
Country/Territory	United States
City	Seattle
Period	18/05/08 → 21/05/08

Cite this

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title = "Predictive timing error calibration technique for RF current-streering DACs",

abstract = "Timing errors become more dominant in dynamic performance in high-resolution Radio Frequency DACs. It consumes a lot of power and area to reduce timing errors below picoseconds. To relax the requirements on circuit design and layout complexity, a predictive timing error calibration technique based on on-chip timing error measurement is demonstrated in this work. Matlab behavior level simulation shows that this on-chip calibration technique can improve the SFDR significantly in a 2GS/s DAC. Simulation results of a phase detector, the key circuit in this calibration technique, are given. The circuit is designed in a CMOS 90nm process.",

author = "Y. Tang and J.A. Hegt and {Roermund, van}, A.H.M.",

year = "2008",

language = "English",

isbn = "978-1-424-41683-7",

pages = "228--231",

booktitle = "Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2008) 18 - 21 May 2008, Seattle, Washington, USA",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "2008 IEEE International Symposium on Circuits and Systems (ISCAS 2008), ISCAS 2008 ; Conference date: 18-05-2008 Through 21-05-2008",

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Tang, Y, Hegt, JA & Roermund, van, AHM 2008, Predictive timing error calibration technique for RF current-streering DACs. in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2008) 18 - 21 May 2008, Seattle, Washington, USA. Institute of Electrical and Electronics Engineers, Piscataway, New Jersy, USA, pp. 228-231, 2008 IEEE International Symposium on Circuits and Systems (ISCAS 2008), Seattle, Washington, United States, 18/05/08.

Predictive timing error calibration technique for RF current-streering DACs. / Tang, Y.; Hegt, J.A.; Roermund, van, A.H.M.
Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2008) 18 - 21 May 2008, Seattle, Washington, USA. Piscataway, New Jersy, USA: Institute of Electrical and Electronics Engineers, 2008. p. 228-231.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Predictive timing error calibration technique for RF current-streering DACs

AU - Tang, Y.

AU - Hegt, J.A.

AU - Roermund, van, A.H.M.

PY - 2008

Y1 - 2008

N2 - Timing errors become more dominant in dynamic performance in high-resolution Radio Frequency DACs. It consumes a lot of power and area to reduce timing errors below picoseconds. To relax the requirements on circuit design and layout complexity, a predictive timing error calibration technique based on on-chip timing error measurement is demonstrated in this work. Matlab behavior level simulation shows that this on-chip calibration technique can improve the SFDR significantly in a 2GS/s DAC. Simulation results of a phase detector, the key circuit in this calibration technique, are given. The circuit is designed in a CMOS 90nm process.

AB - Timing errors become more dominant in dynamic performance in high-resolution Radio Frequency DACs. It consumes a lot of power and area to reduce timing errors below picoseconds. To relax the requirements on circuit design and layout complexity, a predictive timing error calibration technique based on on-chip timing error measurement is demonstrated in this work. Matlab behavior level simulation shows that this on-chip calibration technique can improve the SFDR significantly in a 2GS/s DAC. Simulation results of a phase detector, the key circuit in this calibration technique, are given. The circuit is designed in a CMOS 90nm process.

M3 - Conference contribution

SN - 978-1-424-41683-7

SP - 228

EP - 231

BT - Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2008) 18 - 21 May 2008, Seattle, Washington, USA

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway, New Jersy, USA

T2 - 2008 IEEE International Symposium on Circuits and Systems (ISCAS 2008)

Y2 - 18 May 2008 through 21 May 2008

ER -

Predictive timing error calibration technique for RF current-streering DACs

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