Power supply ramping for quasi-static testing of PLLs

J. Pineda de Gyvez; G. Gronthoud; C. Cenci; M. Posch; T. Burger; M. Koller

doi:10.1109/TEST.2004.1387363

Power supply ramping for quasi-static testing of PLLs

J. Pineda de Gyvez, G. Gronthoud, C. Cenci, M. Posch, T. Burger, M. Koller

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

2 Citations (Scopus)

214 Downloads (Pure)

Abstract

An innovative approach for testing PLLs in open loop-mode is presented. The operational method consists of ramping the PLL's power supply by means of a periodic sawtooth signal. The reference and feedback inputs of the PLL in open-loop mode are connected to the clock reference signal or to ground. Then, the corresponding quiescent current, clock output, and oscillator control voltage signatures are monitored and sampled at specific times. When the power supply is swept, all transistors are forced into various regions of operation causing the sensitivity of the faults to the specific stimulus to be magnified. The developed method of structural testing for PLLs yields high fault coverage results making it a potential and attractive technique for production wafer testing.

Original language	English
Title of host publication	Proceedings of the International Test Conference, 2004, ITC 2004, 26-28 October 2004, Charlotte, New Carolina
Place of Publication	New York
Publisher	Institute of Electrical and Electronics Engineers
Pages	980-987
ISBN (Print)	0-7803-8580-2
DOIs	https://doi.org/10.1109/TEST.2004.1387363
Publication status	Published - 2004

Access to Document

10.1109/TEST.2004.1387363

Metis247727Final published version, 549 KB

Cite this

@inproceedings{ac7b3bca907947afb35fc345b49a3486,

title = "Power supply ramping for quasi-static testing of PLLs",

abstract = "An innovative approach for testing PLLs in open loop-mode is presented. The operational method consists of ramping the PLL's power supply by means of a periodic sawtooth signal. The reference and feedback inputs of the PLL in open-loop mode are connected to the clock reference signal or to ground. Then, the corresponding quiescent current, clock output, and oscillator control voltage signatures are monitored and sampled at specific times. When the power supply is swept, all transistors are forced into various regions of operation causing the sensitivity of the faults to the specific stimulus to be magnified. The developed method of structural testing for PLLs yields high fault coverage results making it a potential and attractive technique for production wafer testing.",

author = "{Pineda de Gyvez}, J. and G. Gronthoud and C. Cenci and M. Posch and T. Burger and M. Koller",

year = "2004",

doi = "10.1109/TEST.2004.1387363",

language = "English",

isbn = "0-7803-8580-2",

pages = "980--987",

booktitle = "Proceedings of the International Test Conference, 2004, ITC 2004, 26-28 October 2004, Charlotte, New Carolina",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

}

Power supply ramping for quasi-static testing of PLLs. / Pineda de Gyvez, J.; Gronthoud, G.; Cenci, C. et al.
Proceedings of the International Test Conference, 2004, ITC 2004, 26-28 October 2004, Charlotte, New Carolina. New York: Institute of Electrical and Electronics Engineers, 2004. p. 980-987.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Power supply ramping for quasi-static testing of PLLs

AU - Pineda de Gyvez, J.

AU - Gronthoud, G.

AU - Cenci, C.

AU - Posch, M.

AU - Burger, T.

AU - Koller, M.

PY - 2004

Y1 - 2004

N2 - An innovative approach for testing PLLs in open loop-mode is presented. The operational method consists of ramping the PLL's power supply by means of a periodic sawtooth signal. The reference and feedback inputs of the PLL in open-loop mode are connected to the clock reference signal or to ground. Then, the corresponding quiescent current, clock output, and oscillator control voltage signatures are monitored and sampled at specific times. When the power supply is swept, all transistors are forced into various regions of operation causing the sensitivity of the faults to the specific stimulus to be magnified. The developed method of structural testing for PLLs yields high fault coverage results making it a potential and attractive technique for production wafer testing.

AB - An innovative approach for testing PLLs in open loop-mode is presented. The operational method consists of ramping the PLL's power supply by means of a periodic sawtooth signal. The reference and feedback inputs of the PLL in open-loop mode are connected to the clock reference signal or to ground. Then, the corresponding quiescent current, clock output, and oscillator control voltage signatures are monitored and sampled at specific times. When the power supply is swept, all transistors are forced into various regions of operation causing the sensitivity of the faults to the specific stimulus to be magnified. The developed method of structural testing for PLLs yields high fault coverage results making it a potential and attractive technique for production wafer testing.

U2 - 10.1109/TEST.2004.1387363

DO - 10.1109/TEST.2004.1387363

M3 - Conference contribution

SN - 0-7803-8580-2

SP - 980

EP - 987

BT - Proceedings of the International Test Conference, 2004, ITC 2004, 26-28 October 2004, Charlotte, New Carolina

PB - Institute of Electrical and Electronics Engineers

CY - New York

ER -

Power supply ramping for quasi-static testing of PLLs

Abstract

Access to Document

Fingerprint

Cite this