Power-scan chain : design for analog testability

A. Zjajo, H.J. Bergveld, R.F. Schuttert, J. Pineda de Gyvez

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

8 Citations (Scopus)
144 Downloads (Pure)

Abstract

This paper reports a design for testability technique, which provides necessary diagnostic capability for signature-based testing of analog circuits. To facilitate this kind of testing, it is preferable to observe the current (or voltage) signatures of individual cores instead of observing the current (or voltage) signature of the whole analog SoC. Therefore, our DfT works like a power-scan chain aimed at turning on/off analog cores in an individual manner, providing an observability means at the core's power and output terminals, and at exciting the core under test. The proposed DfT can be used for engineering pre-characterization as well, and can easily be interfaced to standards like I2C and IEEE 1149.1 TAP controllers. In this paper, we further provide experimental evidence of our approach as applied to an RF device
Original languageEnglish
Title of host publicationProceedings of the IEEE International Test Conference, ITC 2005, 8 November 2005, Austin, Texas
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages4.3-1/8
ISBN (Print)0-7803-9038-5
DOIs
Publication statusPublished - 2005
Eventconference; IEEE Int. Test Conference (ITC 2005); 2005-11-08; 2005-11-10 -
Duration: 8 Nov 200510 Nov 2005

Conference

Conferenceconference; IEEE Int. Test Conference (ITC 2005); 2005-11-08; 2005-11-10
Period8/11/0510/11/05
OtherIEEE Int. Test Conference (ITC 2005)

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