Power reduction through clock gating by symbolic manipulation

J.F.M. Theeuwen

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Original languageEnglish
Title of host publicationVLS I: Integrated Systems on Silicon
EditorsR. Reis, L. Claesen
Place of PublicationLondon
PublisherChapman & Hall
Pages389-400
Number of pages12
ISBN (Print)0-412-82370-5
Publication statusPublished - 1997

Cite this

Theeuwen, J. F. M. (1997). Power reduction through clock gating by symbolic manipulation. In R. Reis, & L. Claesen (Eds.), VLS I: Integrated Systems on Silicon (pp. 389-400). Chapman & Hall.