| Original language | English |
|---|---|
| Title of host publication | VLS I: Integrated Systems on Silicon |
| Editors | R. Reis, L. Claesen |
| Place of Publication | London |
| Publisher | Chapman & Hall |
| Pages | 389-400 |
| Number of pages | 12 |
| ISBN (Print) | 0-412-82370-5 |
| Publication status | Published - 1997 |
Cite this
Theeuwen, J. F. M. (1997). Power reduction through clock gating by symbolic manipulation. In R. Reis, & L. Claesen (Eds.), VLS I: Integrated Systems on Silicon (pp. 389-400). Chapman & Hall.