| Original language | English |
|---|---|
| Title of host publication | VLS I: Integrated Systems on Silicon |
| Editors | R. Reis, L. Claesen |
| Place of Publication | London |
| Publisher | Chapman & Hall |
| Pages | 389-400 |
| Number of pages | 12 |
| ISBN (Print) | 0-412-82370-5 |
| Publication status | Published - 1997 |
Power reduction through clock gating by symbolic manipulation
J.F.M. Theeuwen
Research output: Chapter in Book/Report/Conference proceeding › Chapter › Academic › peer-review
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