This paper presents a procedure for the power-optimal design of high-resolution low-bandwidth switched-capacitor (SC) ¿S modulators (¿SMs). The most power efficient ¿S architecture is identified among single-loop switched-capacitor (SC) feedback (FB) and feed-forward (FF) topologies with different loop order N, oversampling ratio OSR, and quantizer resolution B. Based on the results obtained, an experimental prototype is implemented in a 0.18µm CMOS process, achieving a signal-to-noise ratio (SNR) of 95 dB over a signal bandwidth fBW of 10 kHz. The prototype operates with a 1.28MHz sampling rate and dissipates a total power of 210uW from a 1.8V supply.
|Title of host publication||Proceedings of the 2011 International Workshop on ADC Modelling, Testing and Data Converter Analysis and Design and IEEE 2011 ADC Forum, 30 June - 1 July 2011, Orvieto, Italy|
|Publication status||Published - 2011|
Porrazzo, S., Cannillo, F., Van Hoof, C., Cantatore, E., & Roermund, van, A. H. M. (2011). Power optimization of high-resolution low-bandwidth SC ΔΣ modulators. In K. Havrilla (Ed.), Proceedings of the 2011 International Workshop on ADC Modelling, Testing and Data Converter Analysis and Design and IEEE 2011 ADC Forum, 30 June - 1 July 2011, Orvieto, Italy