Power Optimization for Pipelined ADCs

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Abstract

The developments over the last years in portable and wireless communications have increased the demand for low power circuits and systems. Analog-to-digital converters (ADCs), as essential parts of these systems, should comply with this low power consumption trend. The pipelined ADC in particular is one of the most popular ADC architectures, because it exhibits very good speed and power consumption capabilities and can be easily implemented in digital CMOS technologies. Therefore a systematic study of power optimization for pipelined ADCs became necessary.
Original languageEnglish
Title of host publicationProceedings of the 17th ProRISC, Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2006) 23 - 24 November 2006, Veldhoven, the Netherlands
Place of PublicationUtrecht, the Netherlands
PublisherTechnology Foundation
Pages110-116
ISBN (Print)90-73461-44-8
Publication statusPublished - 2006
Event2006 Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2006) - Veldhoven, Netherlands
Duration: 23 Nov 200624 Nov 2006
Conference number: 17

Conference

Conference2006 Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2006)
Abbreviated titleProRISC 2006
CountryNetherlands
CityVeldhoven
Period23/11/0624/11/06

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  • Cite this

    Zanikopoulos, A., Harpe, P. J. A., Hegt, J. A., & Roermund, van, A. H. M. (2006). Power Optimization for Pipelined ADCs. In Proceedings of the 17th ProRISC, Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2006) 23 - 24 November 2006, Veldhoven, the Netherlands (pp. 110-116). Utrecht, the Netherlands: Technology Foundation.