In this work, a new library is developed for 28-nm FDSOI CMOS technology. The new library is optimized for near-threshold operating voltage of 0.4V by balancing the pull-up/ pull-down networks (PUN/PDN) of logic gates, focusing on device sizing and exploiting poly-biasing feature. With the new library, up to 38% of leakage power consumption savings and up to 9% of dynamic power consumption savings are achieved for a variety of ITC benchmark circuits and an ARM Cortex-M0 as compared to the existing library. Combining the newly developed library with the existing libraries reduces the power consumption even more without any performance and area penalty. Monte Carlo simulations on the critical path delay of the ARM Cortex- M0 shows that the mean and standard deviation decreased by up to 8% and 22%, respectively, improving speed and robustness.
|Title of host publication||2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019|
|Publisher||Institute of Electrical and Electronics Engineers|
|Publication status||Published - 14 Oct 2019|
|Event||2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019 - San Jose, United States|
Duration: 14 Oct 2019 → 17 Oct 2019
|Conference||2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019|
|Period||14/10/19 → 17/10/19|