Post-silicon validation of yield-aware analog circuit synthesis

Engin Afacan, Gönenç Berkol, Günhan Dündar

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Abstract

Analog/RF circuit design automation tools have become more popular in recent years. Conventionally, evolutionary algorithms are employed during circuit sizing and layout generation processes; thus, time to design can be considerably reduced. Furthermore, yield-aware analog circuit design automation tools have been developed by integrating variability analysis with the optimization. Previous works have mostly focused on improving the efficiency of optimization tools without sacrificing the accuracy. However, the accuracy of design automation tools is still argumentative since they are validated either at the pre- or post- layout level. But, in practice, post-silicon measurement is mandatory in order to verify the robustness of synthesis tools. To our best knowledge, there is no implementation and verification of yield-aware circuit sizing tools in the literature. In this study, a yield-aware circuit sizing tool is validated on silicon. For that purpose, two different OTA circuits were optimized using a yield-aware circuit sizing tool, a test chip was designed, taped-out, characterized, and results were compared with the results generated by the optimizer.

Original languageEnglish
Title of host publicationSMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages245-248
Number of pages4
ISBN (Electronic)978-1-7281-1201-5
DOIs
Publication statusPublished - 1 Jul 2019
Event16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2019 - Lausanne, Switzerland
Duration: 15 Jul 201918 Jul 2019

Conference

Conference16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2019
CountrySwitzerland
CityLausanne
Period15/07/1918/07/19

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