Post-silicon validation of yield-aware analog circuit synthesis

Engin Afacan, Gönenç Berkol, Günhan Dündar

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Abstract

Analog/RF circuit design automation tools have become more popular in recent years. Conventionally, evolutionary algorithms are employed during circuit sizing and layout generation processes; thus, time to design can be considerably reduced. Furthermore, yield-aware analog circuit design automation tools have been developed by integrating variability analysis with the optimization. Previous works have mostly focused on improving the efficiency of optimization tools without sacrificing the accuracy. However, the accuracy of design automation tools is still argumentative since they are validated either at the pre- or post- layout level. But, in practice, post-silicon measurement is mandatory in order to verify the robustness of synthesis tools. To our best knowledge, there is no implementation and verification of yield-aware circuit sizing tools in the literature. In this study, a yield-aware circuit sizing tool is validated on silicon. For that purpose, two different OTA circuits were optimized using a yield-aware circuit sizing tool, a test chip was designed, taped-out, characterized, and results were compared with the results generated by the optimizer.

LanguageEnglish
Title of host publicationSMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages245-248
Number of pages4
ISBN (Electronic)978-1-7281-1201-5
DOIs
StatePublished - 1 Jul 2019
Event16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2019 - Lausanne, Switzerland
Duration: 15 Jul 201918 Jul 2019

Conference

Conference16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2019
CountrySwitzerland
CityLausanne
Period15/07/1918/07/19

Fingerprint

analog circuits
Analog Circuits
Analog circuits
Silicon
Synthesis
sizing
silicon
synthesis
Design Automation
Networks (circuits)
automation
Automation
Circuit Design
layouts
Layout
optimization
Optimization
Evolutionary algorithms
Evolutionary Algorithms
Chip

Cite this

Afacan, E., Berkol, G., & Dündar, G. (2019). Post-silicon validation of yield-aware analog circuit synthesis. In SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings (pp. 245-248). [8795252] Piscataway: Institute of Electrical and Electronics Engineers. DOI: 10.1109/SMACD.2019.8795252
Afacan, Engin ; Berkol, Gönenç ; Dündar, Günhan. / Post-silicon validation of yield-aware analog circuit synthesis. SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings. Piscataway : Institute of Electrical and Electronics Engineers, 2019. pp. 245-248
@inproceedings{45402fb3f761401380c9fa04cc41f3b7,
title = "Post-silicon validation of yield-aware analog circuit synthesis",
abstract = "Analog/RF circuit design automation tools have become more popular in recent years. Conventionally, evolutionary algorithms are employed during circuit sizing and layout generation processes; thus, time to design can be considerably reduced. Furthermore, yield-aware analog circuit design automation tools have been developed by integrating variability analysis with the optimization. Previous works have mostly focused on improving the efficiency of optimization tools without sacrificing the accuracy. However, the accuracy of design automation tools is still argumentative since they are validated either at the pre- or post- layout level. But, in practice, post-silicon measurement is mandatory in order to verify the robustness of synthesis tools. To our best knowledge, there is no implementation and verification of yield-aware circuit sizing tools in the literature. In this study, a yield-aware circuit sizing tool is validated on silicon. For that purpose, two different OTA circuits were optimized using a yield-aware circuit sizing tool, a test chip was designed, taped-out, characterized, and results were compared with the results generated by the optimizer.",
author = "Engin Afacan and G{\"o}nen{\cc} Berkol and G{\"u}nhan D{\"u}ndar",
year = "2019",
month = "7",
day = "1",
doi = "10.1109/SMACD.2019.8795252",
language = "English",
pages = "245--248",
booktitle = "SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings",
publisher = "Institute of Electrical and Electronics Engineers",
address = "United States",

}

Afacan, E, Berkol, G & Dündar, G 2019, Post-silicon validation of yield-aware analog circuit synthesis. in SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings., 8795252, Institute of Electrical and Electronics Engineers, Piscataway, pp. 245-248, 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2019, Lausanne, Switzerland, 15/07/19. DOI: 10.1109/SMACD.2019.8795252

Post-silicon validation of yield-aware analog circuit synthesis. / Afacan, Engin; Berkol, Gönenç; Dündar, Günhan.

SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings. Piscataway : Institute of Electrical and Electronics Engineers, 2019. p. 245-248 8795252.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

TY - GEN

T1 - Post-silicon validation of yield-aware analog circuit synthesis

AU - Afacan,Engin

AU - Berkol,Gönenç

AU - Dündar,Günhan

PY - 2019/7/1

Y1 - 2019/7/1

N2 - Analog/RF circuit design automation tools have become more popular in recent years. Conventionally, evolutionary algorithms are employed during circuit sizing and layout generation processes; thus, time to design can be considerably reduced. Furthermore, yield-aware analog circuit design automation tools have been developed by integrating variability analysis with the optimization. Previous works have mostly focused on improving the efficiency of optimization tools without sacrificing the accuracy. However, the accuracy of design automation tools is still argumentative since they are validated either at the pre- or post- layout level. But, in practice, post-silicon measurement is mandatory in order to verify the robustness of synthesis tools. To our best knowledge, there is no implementation and verification of yield-aware circuit sizing tools in the literature. In this study, a yield-aware circuit sizing tool is validated on silicon. For that purpose, two different OTA circuits were optimized using a yield-aware circuit sizing tool, a test chip was designed, taped-out, characterized, and results were compared with the results generated by the optimizer.

AB - Analog/RF circuit design automation tools have become more popular in recent years. Conventionally, evolutionary algorithms are employed during circuit sizing and layout generation processes; thus, time to design can be considerably reduced. Furthermore, yield-aware analog circuit design automation tools have been developed by integrating variability analysis with the optimization. Previous works have mostly focused on improving the efficiency of optimization tools without sacrificing the accuracy. However, the accuracy of design automation tools is still argumentative since they are validated either at the pre- or post- layout level. But, in practice, post-silicon measurement is mandatory in order to verify the robustness of synthesis tools. To our best knowledge, there is no implementation and verification of yield-aware circuit sizing tools in the literature. In this study, a yield-aware circuit sizing tool is validated on silicon. For that purpose, two different OTA circuits were optimized using a yield-aware circuit sizing tool, a test chip was designed, taped-out, characterized, and results were compared with the results generated by the optimizer.

UR - http://www.scopus.com/inward/record.url?scp=85071598255&partnerID=8YFLogxK

U2 - 10.1109/SMACD.2019.8795252

DO - 10.1109/SMACD.2019.8795252

M3 - Conference contribution

SP - 245

EP - 248

BT - SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

ER -

Afacan E, Berkol G, Dündar G. Post-silicon validation of yield-aware analog circuit synthesis. In SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings. Piscataway: Institute of Electrical and Electronics Engineers. 2019. p. 245-248. 8795252. Available from, DOI: 10.1109/SMACD.2019.8795252