Abstract
In IC manufacturing, lithographic scanners expose a circuit pattern onto a semiconductor wafer by means of an optical system. The stage holding the wafer must have a scanning position accuracy of only a few nanometers to support imaging and overlay requirements. In the past 10 years, stage acceleration, position error and settling time have all improved 5-8 times. Compared to lithographic steppers of 25 years ago, the number of controlled stage axes has grown from 3 (analog) to 50 (high-speed digital).
| Original language | English |
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| Title of host publication | Proceedings of the ASPE 2013 Spring Topical Meeting MIT Laboratory for Manufacturing and Productivity Annual Summit, 21-23 April 2013, Cambridge, Massachusetts |
| Place of Publication | Raleigh |
| Publisher | American Society of Precision Engineering (ASPE) |
| Pages | 7-12 |
| Publication status | Published - 2013 |
| Event | ASPE 2013 Spring Topical Meeting MIT Laboratory for Manufacturing and Productivity Annual Summit - Duration: 21 Apr 2013 → 23 Apr 2013 |
Conference
| Conference | ASPE 2013 Spring Topical Meeting MIT Laboratory for Manufacturing and Productivity Annual Summit |
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| Period | 21/04/13 → 23/04/13 |