Abstract
A simulated annealing-based algorithm is presented for the placement of shapeable blocks for IC layouts. The algorithm minimizes both the enveloping area and the estimated total wire length of a set of blocks interconnected by nets. The size of the blocks may vary within limits. Overlap among blocks is allowed but increasingly penalized as the optimization process continues. The presence of overlap is found to be essential for obtaining good solutions to the placement problem. The various terms in the cost function are discussed. In addition to the sequential implementation, the authors present a parallel implementation of the placement algorithm on an experimental multiprocessor architecture using a clustered simulated annealing algorithm. It is concluded that the placement algorithm performs well for both the sequential and parallel implementation.
Original language | English |
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Pages (from-to) | 1-22 |
Number of pages | 22 |
Journal | Philips Journal of Research |
Volume | 43 |
Issue number | 1 |
Publication status | Published - 1988 |
Externally published | Yes |