Pipelined Architecture for Soft-Decision Iterative Projection Aggregation Decoding for RM Codes

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The recently proposed recursive projection-aggregation (RPA) decoding algorithm for Reed-Muller codes has received significant attention as it provides near-ML decoding performance at reasonable complexity for short codes. However, its complicated structure makes it unsuitable for hardware implementation. Iterative projection-aggregation (IPA) decoding is a modified version of RPA decoding that simplifies the hardware implementation. In this work, we present a flexible hardware architecture for the IPA decoder that can be configured from fully-sequential to fully-parallel, thus making it suitable for a wide range of applications with different constraints and resource budgets. Our simulation and implementation results show that the IPA decoder has 41% lower area consumption, 44% lower latency, four times higher throughput, but currently seven times higher power consumption for a code with a block length of 128 and information length of 29 compared to a state-of-the-art polar successive cancellation list (SCL) decoder with comparable decoding performance.

Original languageEnglish
Article number10236524
Pages (from-to)5468-5481
Number of pages14
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Issue number12
Publication statusPublished - 1 Dec 2023


This work was supported by the Eindhoven University of Technology.

FundersFunder number
Eindhoven University of Technology


    • Linear codes
    • Complexity theory
    • Hardware
    • IPA
    • Iterative decoding
    • Maximum likelihood decoding
    • pipelined architecture
    • Reed-Muller codes
    • RPA
    • Ultra reliable low latency communication


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