Phase noise in frequency divider circuits

M. Apostolidou, P.G.M. Baltus, C.S. Vaucher

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

8 Citations (Scopus)
853 Downloads (Pure)

Abstract

We identify limitations of the models for phase noise in frequency dividers by Egan and by Phillips and present a new model applicable to both high frequency and low power frequency divider design. Further, we design both synchronous and asynchronous frequency divider test chips that allow us to observe experimentally the effects of noise accumulation, sampling frequency and biasing conditions on the total phase noise performance of frequency dividers. We use our measurements to validate the simulated values obtained by time domain phase noise analysis offered by the commercial simulator Spectre RF. The measured data show good agreement with the simulation results
Original languageEnglish
Title of host publicationProceedings of 2008 IEEE International Symposium on Circuits and Systems : Seattle, WA, 18 - 21 May 2008
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages2538-2541
ISBN (Print)978-1-4244-1683-7
DOIs
Publication statusPublished - 2008

Fingerprint Dive into the research topics of 'Phase noise in frequency divider circuits'. Together they form a unique fingerprint.

Cite this