Phase noise in frequency divider circuits

M. Apostolidou; P.G.M. Baltus; C.S. Vaucher

doi:10.1109/ISCAS.2008.4541973

Phase noise in frequency divider circuits

M. Apostolidou, P.G.M. Baltus, C.S. Vaucher

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

9 Citations (Scopus)

1912 Downloads (Pure)

Abstract

We identify limitations of the models for phase noise in frequency dividers by Egan and by Phillips and present a new model applicable to both high frequency and low power frequency divider design. Further, we design both synchronous and asynchronous frequency divider test chips that allow us to observe experimentally the effects of noise accumulation, sampling frequency and biasing conditions on the total phase noise performance of frequency dividers. We use our measurements to validate the simulated values obtained by time domain phase noise analysis offered by the commercial simulator Spectre RF. The measured data show good agreement with the simulation results

Original language	English
Title of host publication	Proceedings of 2008 IEEE International Symposium on Circuits and Systems : Seattle, WA, 18 - 21 May 2008
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	2538-2541
ISBN (Print)	978-1-4244-1683-7
DOIs	https://doi.org/10.1109/ISCAS.2008.4541973
Publication status	Published - 2008

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10.1109/ISCAS.2008.4541973

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@inproceedings{e2bcdb1cd1994ea1bac0711253da0f3a,

title = "Phase noise in frequency divider circuits",

abstract = "We identify limitations of the models for phase noise in frequency dividers by Egan and by Phillips and present a new model applicable to both high frequency and low power frequency divider design. Further, we design both synchronous and asynchronous frequency divider test chips that allow us to observe experimentally the effects of noise accumulation, sampling frequency and biasing conditions on the total phase noise performance of frequency dividers. We use our measurements to validate the simulated values obtained by time domain phase noise analysis offered by the commercial simulator Spectre RF. The measured data show good agreement with the simulation results",

author = "M. Apostolidou and P.G.M. Baltus and C.S. Vaucher",

year = "2008",

doi = "10.1109/ISCAS.2008.4541973",

language = "English",

isbn = "978-1-4244-1683-7",

pages = "2538--2541",

booktitle = "Proceedings of 2008 IEEE International Symposium on Circuits and Systems : Seattle, WA, 18 - 21 May 2008",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

}

Phase noise in frequency divider circuits. / Apostolidou, M.; Baltus, P.G.M.; Vaucher, C.S.
Proceedings of 2008 IEEE International Symposium on Circuits and Systems : Seattle, WA, 18 - 21 May 2008. Piscataway: Institute of Electrical and Electronics Engineers, 2008. p. 2538-2541.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Phase noise in frequency divider circuits

AU - Apostolidou, M.

AU - Baltus, P.G.M.

AU - Vaucher, C.S.

PY - 2008

Y1 - 2008

N2 - We identify limitations of the models for phase noise in frequency dividers by Egan and by Phillips and present a new model applicable to both high frequency and low power frequency divider design. Further, we design both synchronous and asynchronous frequency divider test chips that allow us to observe experimentally the effects of noise accumulation, sampling frequency and biasing conditions on the total phase noise performance of frequency dividers. We use our measurements to validate the simulated values obtained by time domain phase noise analysis offered by the commercial simulator Spectre RF. The measured data show good agreement with the simulation results

AB - We identify limitations of the models for phase noise in frequency dividers by Egan and by Phillips and present a new model applicable to both high frequency and low power frequency divider design. Further, we design both synchronous and asynchronous frequency divider test chips that allow us to observe experimentally the effects of noise accumulation, sampling frequency and biasing conditions on the total phase noise performance of frequency dividers. We use our measurements to validate the simulated values obtained by time domain phase noise analysis offered by the commercial simulator Spectre RF. The measured data show good agreement with the simulation results

U2 - 10.1109/ISCAS.2008.4541973

DO - 10.1109/ISCAS.2008.4541973

M3 - Conference contribution

SN - 978-1-4244-1683-7

SP - 2538

EP - 2541

BT - Proceedings of 2008 IEEE International Symposium on Circuits and Systems : Seattle, WA, 18 - 21 May 2008

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

ER -

Phase noise in frequency divider circuits

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