Performance exploration of partially connected 3D NoCs under manufacturing variability

Anelise Kologeski; Fernanda Lima Kastensmidt; Vianney Lapotre; Abdoulaye Gamatié; Gilles Sassatelli; Aida Todri-Sanial

doi:10.1109/NEWCAS.2014.6933985

Performance exploration of partially connected 3D NoCs under manufacturing variability

Anelise Kologeski, Fernanda Lima Kastensmidt, Vianney Lapotre, Abdoulaye Gamatié, Gilles Sassatelli, Aida Todri-Sanial

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

4 Citations (Scopus)

Abstract

Several Through-Silicon-Vias (TSVs) may present resistive and open defects due to 3D manufacture variability. This paper advocates the use of 3D Network-on-Chip (NoC) with asynchronous communication interfaces to cope with significant variations in TSV propagation delays. The technique uses serial communication in the vertical channels to reduce the number of TSVs. Based on a representative delay distribution, we compare the average performance considering a non-defective 3D NoC, one with resistive defective TSVs and one with resistive and open defective TSVs. Results show that it is better to adapt the interfaces to cope with large margins of delay than to avoid TSVs by using adaptive routing.

Original language	English
Title of host publication	2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS)
Publisher	Institute of Electrical and Electronics Engineers
Pages	61-64
Number of pages	4
ISBN (Electronic)	978-1-4799-4885-7
DOIs	https://doi.org/10.1109/NEWCAS.2014.6933985
Publication status	Published - 2014
Externally published	Yes

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10.1109/NEWCAS.2014.6933985

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Kologeski, A., Kastensmidt, F. L., Lapotre, V., Gamatié, A., Sassatelli, G., & Todri-Sanial, A. (2014). Performance exploration of partially connected 3D NoCs under manufacturing variability. In 2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS) (pp. 61-64). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/NEWCAS.2014.6933985

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title = "Performance exploration of partially connected 3D NoCs under manufacturing variability",

abstract = "Several Through-Silicon-Vias (TSVs) may present resistive and open defects due to 3D manufacture variability. This paper advocates the use of 3D Network-on-Chip (NoC) with asynchronous communication interfaces to cope with significant variations in TSV propagation delays. The technique uses serial communication in the vertical channels to reduce the number of TSVs. Based on a representative delay distribution, we compare the average performance considering a non-defective 3D NoC, one with resistive defective TSVs and one with resistive and open defective TSVs. Results show that it is better to adapt the interfaces to cope with large margins of delay than to avoid TSVs by using adaptive routing.",

author = "Anelise Kologeski and Kastensmidt, {Fernanda Lima} and Vianney Lapotre and Abdoulaye Gamati{\'e} and Gilles Sassatelli and Aida Todri-Sanial",

year = "2014",

doi = "10.1109/NEWCAS.2014.6933985",

language = "English",

pages = "61--64",

booktitle = "2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS)",

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Performance exploration of partially connected 3D NoCs under manufacturing variability. / Kologeski, Anelise; Kastensmidt, Fernanda Lima; Lapotre, Vianney et al.
2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS). Institute of Electrical and Electronics Engineers, 2014. p. 61-64.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

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AU - Kologeski, Anelise

AU - Kastensmidt, Fernanda Lima

AU - Lapotre, Vianney

AU - Gamatié, Abdoulaye

AU - Sassatelli, Gilles

AU - Todri-Sanial, Aida

PY - 2014

Y1 - 2014

N2 - Several Through-Silicon-Vias (TSVs) may present resistive and open defects due to 3D manufacture variability. This paper advocates the use of 3D Network-on-Chip (NoC) with asynchronous communication interfaces to cope with significant variations in TSV propagation delays. The technique uses serial communication in the vertical channels to reduce the number of TSVs. Based on a representative delay distribution, we compare the average performance considering a non-defective 3D NoC, one with resistive defective TSVs and one with resistive and open defective TSVs. Results show that it is better to adapt the interfaces to cope with large margins of delay than to avoid TSVs by using adaptive routing.

AB - Several Through-Silicon-Vias (TSVs) may present resistive and open defects due to 3D manufacture variability. This paper advocates the use of 3D Network-on-Chip (NoC) with asynchronous communication interfaces to cope with significant variations in TSV propagation delays. The technique uses serial communication in the vertical channels to reduce the number of TSVs. Based on a representative delay distribution, we compare the average performance considering a non-defective 3D NoC, one with resistive defective TSVs and one with resistive and open defective TSVs. Results show that it is better to adapt the interfaces to cope with large margins of delay than to avoid TSVs by using adaptive routing.

U2 - 10.1109/NEWCAS.2014.6933985

DO - 10.1109/NEWCAS.2014.6933985

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BT - 2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS)

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ER -

Performance exploration of partially connected 3D NoCs under manufacturing variability

Abstract

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