Performance-efficient architecture for free-viewpoint 3DTV receiver

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This paper presents algorithmic and architectural solutions for a free-viewpoint 3DTV receiver system. We describe our rendering algorithm and evaluate performance-related challenges in mapping of the algorithm on a receiver board of which the architecture is outlined. It is found that the required processing load exceeds the provisioning of dual Virtex5 FPGAs. We develop several mapping optimizations to fit the rendering algorithm into a platform.
Original languageEnglish
Title of host publicationProceedings of the 28th International Conference on Consumer Electronics (ICCE), 9-13 January 2010, Las Vegas, Nevada
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
ISBN (Electronic)978-1-4244-4316-1
ISBN (Print)978-1-4244-4314-7
Publication statusPublished - 2010
Event2010 IEEE International Conference on Consumer Electronics, ICCE 2010 - Las Vegas, United States
Duration: 11 Jan 201013 Jan 2010


Conference2010 IEEE International Conference on Consumer Electronics, ICCE 2010
Abbreviated titleICCE 2010
Country/TerritoryUnited States
CityLas Vegas
Other“Green Consumer Electronic Technologies”


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