Performance-efficient architecture for free-viewpoint 3DTV receiver

E. Bondarev; S. Zinger; P.H.N. With, de

doi:10.1109/ICCE.2010.5418923

Performance-efficient architecture for free-viewpoint 3DTV receiver

E. Bondarev, S. Zinger, P.H.N. With, de

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

10 Citations (Scopus)

186 Downloads (Pure)

Abstract

This paper presents algorithmic and architectural solutions for a free-viewpoint 3DTV receiver system. We describe our rendering algorithm and evaluate performance-related challenges in mapping of the algorithm on a receiver board of which the architecture is outlined. It is found that the required processing load exceeds the provisioning of dual Virtex5 FPGAs. We develop several mapping optimizations to fit the rendering algorithm into a platform.

Original language	English
Title of host publication	Proceedings of the 28th International Conference on Consumer Electronics (ICCE), 9-13 January 2010, Las Vegas, Nevada
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	65-66
ISBN (Electronic)	978-1-4244-4316-1
ISBN (Print)	978-1-4244-4314-7
DOIs	https://doi.org/10.1109/ICCE.2010.5418923
Publication status	Published - 2010
Event	2010 IEEE International Conference on Consumer Electronics, ICCE 2010 - Las Vegas, United States Duration: 11 Jan 2010 → 13 Jan 2010

Conference

Conference	2010 IEEE International Conference on Consumer Electronics, ICCE 2010
Abbreviated title	ICCE 2010
Country/Territory	United States
City	Las Vegas
Period	11/01/10 → 13/01/10
Other	“Green Consumer Electronic Technologies”

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10.1109/ICCE.2010.5418923

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title = "Performance-efficient architecture for free-viewpoint 3DTV receiver",

abstract = "This paper presents algorithmic and architectural solutions for a free-viewpoint 3DTV receiver system. We describe our rendering algorithm and evaluate performance-related challenges in mapping of the algorithm on a receiver board of which the architecture is outlined. It is found that the required processing load exceeds the provisioning of dual Virtex5 FPGAs. We develop several mapping optimizations to fit the rendering algorithm into a platform.",

author = "E. Bondarev and S. Zinger and {With, de}, P.H.N.",

year = "2010",

doi = "10.1109/ICCE.2010.5418923",

language = "English",

isbn = "978-1-4244-4314-7",

pages = "65--66",

booktitle = "Proceedings of the 28th International Conference on Consumer Electronics (ICCE), 9-13 January 2010, Las Vegas, Nevada",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "2010 IEEE International Conference on Consumer Electronics, ICCE 2010, ICCE 2010 ; Conference date: 11-01-2010 Through 13-01-2010",

}

Bondarev, E , Zinger, S & With, de, PHN 2010, Performance-efficient architecture for free-viewpoint 3DTV receiver. in Proceedings of the 28th International Conference on Consumer Electronics (ICCE), 9-13 January 2010, Las Vegas, Nevada. Institute of Electrical and Electronics Engineers, Piscataway, pp. 65-66, 2010 IEEE International Conference on Consumer Electronics, ICCE 2010, Las Vegas, Nevada, United States, 11/01/10. https://doi.org/10.1109/ICCE.2010.5418923

Performance-efficient architecture for free-viewpoint 3DTV receiver. / Bondarev, E.; Zinger, S.; With, de, P.H.N.
Proceedings of the 28th International Conference on Consumer Electronics (ICCE), 9-13 January 2010, Las Vegas, Nevada. Piscataway: Institute of Electrical and Electronics Engineers, 2010. p. 65-66.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AU - Zinger, S.

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N2 - This paper presents algorithmic and architectural solutions for a free-viewpoint 3DTV receiver system. We describe our rendering algorithm and evaluate performance-related challenges in mapping of the algorithm on a receiver board of which the architecture is outlined. It is found that the required processing load exceeds the provisioning of dual Virtex5 FPGAs. We develop several mapping optimizations to fit the rendering algorithm into a platform.

AB - This paper presents algorithmic and architectural solutions for a free-viewpoint 3DTV receiver system. We describe our rendering algorithm and evaluate performance-related challenges in mapping of the algorithm on a receiver board of which the architecture is outlined. It is found that the required processing load exceeds the provisioning of dual Virtex5 FPGAs. We develop several mapping optimizations to fit the rendering algorithm into a platform.

U2 - 10.1109/ICCE.2010.5418923

DO - 10.1109/ICCE.2010.5418923

M3 - Conference contribution

SN - 978-1-4244-4314-7

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EP - 66

BT - Proceedings of the 28th International Conference on Consumer Electronics (ICCE), 9-13 January 2010, Las Vegas, Nevada

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

T2 - 2010 IEEE International Conference on Consumer Electronics, ICCE 2010

Y2 - 11 January 2010 through 13 January 2010

ER -

Performance-efficient architecture for free-viewpoint 3DTV receiver

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