Parasitic inductive coupling of integrated circuits with their environment

D. Ioan, G. Ciuprina, W.H.A. Schilders

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Abstract

This paper describes an original methodology for the modeling of parasitic inductive couplings. The key idea is the use of magnetic hooks which are gates for magnetic fluxes that cross conductive loops and consequently induce parasitic voltages, thus disturbing the signal integrity. The multiple connected domains of integrated circuits are modeled by a Magneto-Electric-Equivalent-Circuit (MEEC), consisting of two mutual coupled circuits, an electric and magnetic one. Magnetic hooks are the externally connected nodes of the magnetic circuit. © 2014 The Institute of Electronics, Information and Communication Engineer. Keywords: Chip; Computational Electromagnetics; IC & Semiconductor EMC; Numerical Modeling; Signal Integrity
Original languageEnglish
Title of host publication2014 International Symposium on Electromagnetic CompatibiIity (EMC 2014, Tokyo, Japan, May 12-16, 2014)
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages565-568
ISBN (Print)978-488552287-1
Publication statusPublished - 2014
Event2014 International Symposium on Electromagnetic CompatibiIity (EMC 2014/Tokyo) - Tokyo, Japan
Duration: 12 May 201416 May 2014

Conference

Conference2014 International Symposium on Electromagnetic CompatibiIity (EMC 2014/Tokyo)
Abbreviated titleEMC'14/Tokyo
CountryJapan
CityTokyo
Period12/05/1416/05/14

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    Ioan, D., Ciuprina, G., & Schilders, W. H. A. (2014). Parasitic inductive coupling of integrated circuits with their environment. In 2014 International Symposium on Electromagnetic CompatibiIity (EMC 2014, Tokyo, Japan, May 12-16, 2014) (pp. 565-568). Institute of Electrical and Electronics Engineers.