Abstract
This paper describes an original methodology for the modeling of parasitic inductive couplings. The key idea is the use of magnetic hooks which are gates for magnetic fluxes that cross conductive loops and consequently induce parasitic voltages, thus disturbing the signal integrity. The multiple connected domains of integrated circuits are modeled by a Magneto-Electric-Equivalent-Circuit (MEEC), consisting of two mutual coupled circuits, an electric and magnetic one. Magnetic hooks are the externally connected nodes of the magnetic circuit. © 2014 The Institute of Electronics, Information and Communication Engineer.
Keywords: Chip; Computational Electromagnetics; IC & Semiconductor EMC; Numerical Modeling; Signal Integrity
| Original language | English |
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| Title of host publication | 2014 International Symposium on Electromagnetic CompatibiIity (EMC 2014, Tokyo, Japan, May 12-16, 2014) |
| Place of Publication | Piscataway |
| Publisher | Institute of Electrical and Electronics Engineers |
| Pages | 565-568 |
| ISBN (Print) | 978-488552287-1 |
| Publication status | Published - 2014 |
| Event | 2014 International Symposium on Electromagnetic CompatibiIity (EMC 2014/Tokyo) - Tokyo, Japan Duration: 12 May 2014 → 16 May 2014 |
Conference
| Conference | 2014 International Symposium on Electromagnetic CompatibiIity (EMC 2014/Tokyo) |
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| Abbreviated title | EMC'14/Tokyo |
| Country/Territory | Japan |
| City | Tokyo |
| Period | 12/05/14 → 16/05/14 |