Parallel current-steering D/A Converters for flexibility and smartness

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Abstract

This paper presents a DAC architecture built on parallel current-steering sub-DAC entities. Two main novelties are explored: flexibility and smartness. Firstly, a number of available operating modes (op-modes) can set the overall DAC performance and functionality. These op-modes transfer some of the important design trade-offs to the end-user and constitute the DAC flexibility. The main examples include: resolution-power-number of DACs, static-dynamic performance, etc. Secondly, specific signal processing techniques become possible. The main examples of such techniques include: full self-calibration, cancellation of harmonic distortion (HD) components, and linearity improvement through redundancy. This paper concentrates on a method to suppress undesired HD components through DA processing of phase shifted replicas of the main input signal. The presented theoretical concepts are realized in a 14-bit DAC built from 4 parallel 12-bit sub-DACs. Transistor simulations and a layout design are also presented. The demonstrated flexibility characteristics of the new DAC architecture make the discussed concepts particularly suitable for FPGA integration.
Original languageEnglish
Title of host publicationProceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2007) 27 - 30 May 2007, New Orleans, Louisiana, USA
Place of PublicationPiscataway, New Jersey, USA
PublisherInstitute of Electrical and Electronics Engineers
Pages1465-1468
ISBN (Print)1-4244-0920-9
DOIs
Publication statusPublished - 2007
Event2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007) - New Orleans, United States
Duration: 27 May 200730 May 2007
http://www.iscas2007.org/

Conference

Conference2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007)
Abbreviated titleISCAS 2007
CountryUnited States
CityNew Orleans
Period27/05/0730/05/07
Internet address

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