Overcoming the limitations of the traditional loop parallelization

I. Karkowski, H. Corporaal

Research output: Contribution to journalArticleAcademicpeer-review

5 Citations (Scopus)


Previous research has shown existence of a huge potential of the coarse-grain parallelism in programs. This parallelism is however not always easy to exploit, especially, when applying today's parallelizing compilers to typical applications from the "embedded" domain. This is mainly due to the deficiencies of the static data dependency analysis they relay on. This paper investigates the potentials of the loops parallelization techniques using dynamic loop analysis techniques. For a set of "embedded" benchmarks (including an MPEG-2 encoder) ˜4 times more loops could be parallelized, in comparison with a state-of-the-art compiler (SUIF [S.P. Amarasinghe et al., Multiprocessors From a Software Perspective, IEEE micro, June 1996, pp. 52–61]), leading to average speed-ups of 2.85 (on a four-processor system). Dynamic analysis is however not "full-proof" — we intend to use it exclusively in cases when static analysis fails to give any answer, and only if the user asserts its applicability. Author Keywords: Multiprocessing; Loop parallelization techniques; Data dependency analysis; High performance embedded system design
Original languageEnglish
Pages (from-to)407-416
Number of pages10
JournalFuture Generation Computer Systems
Issue number4-5
Publication statusPublished - 1998


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