Optimization of Cu Low-k bond pad designs to improve mechanical robustness using the Area Release Energy method

In the development of present and future CMOS technologies (CMOS065 and beyond) for microelectroniccomponents the combination of state-of-the-artmodeling techniques and experimental testing is crucialand provides a challenge to address the thermomechanical reliability issues and the demand for shorter time-to-market by the industry[1]. Nowadays these modeling techniques often involve the construction of very detailed Cu Low-k IC structures, which is still very time-consuming and computationally demanding. This paper adresses an alternative modeling strategy that intends to gain fundamental insights andunderstanding of the mechanisms that have an impact onthe thermo-mechanical reliability of a Cu Low-k device.As an example the relation between the metal densities of the various layers in a typical Cu Low-k IC bond padstructure and the Area Release Energy (ARE) criterion [2] has been investigated. The modeling and computational effort have been considerably limited by building a simplified twodimensional bond pad model. This model is constructed such that it is well capable to reveal the impact on the thermo-mechanical reliability and such that it is still representative for the behaviour of advanced Cu Low-k structures. When optimizing the bond pad towards lower ARE levels for better mechanical robustness the impact ofthe metal density within the BE layers is evident.Furthermore, it shows that the metal density in a single layer does not only affect the ARE level in that specific layer, but it also influences the ARE profile within the entire stack. Clearly, the presented modeling strategy is suitable to identify the design parameters that play an important rolewhen optimizing the thermo-mechanical performance ofadvanced Cu Low-k structures. In combination withexperimental tests (e.g. industrial qualification tests, interface strength measurements, etc.) it may provide a robust tool to further improve and ensure the reliability of present and future IC bond pad structures.