Optimal interconnect ATPG under a ground-bounce constraint

H.D.L. Hollmann, E.J. Marinissen, B. Vermeulen

Research output: Chapter in Book/Report/Conference proceedingChapterAcademicpeer-review

Abstract

In order to prevent ground bounce, automatic test pattern generation (ATPG) algorithms for wire interconnects have recently been extended with the capability to restrict the maximum Hamming distance between any two consecutive test patterns to a user-defined integer, referred to as simultaneously-switching outputs limit (SSOL). The conventional approach to meet this SSOL constraint is to insert additional test patterns between consecutive test patterns if their Hamming distance is too large; this approach often leads to many more test patterns than strictly necessary. This paper presents an algorithm that generates, for a user-defined number of interconnect wires, a minimal set of test patterns that respect a user-defined SSOL constraint. Experimental results show that, in comparison to the conventional approach, our algorithm leads to a significant reduction in the test pattern count and corresponding test application time. For example, for problem instances with 5000, 6000, 7000, and 8000 wires, the algorithm reduces the corresponding test application time on average with 45%.
Original languageEnglish
Title of host publicationInternational Test Conference, 2003. Proceedings. ITC 2003
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages369-378
ISBN (Print)0-7803-8106-8
DOIs
Publication statusPublished - 2003
Externally publishedYes
Event2003 International Test Conference (ITC 2003) - Charlotte, United States
Duration: 30 Sep 20032 Oct 2003

Conference

Conference2003 International Test Conference (ITC 2003)
Abbreviated titleITC 2003
Country/TerritoryUnited States
CityCharlotte
Period30/09/032/10/03

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