On using rectangle packing for SOC Wrapper/TAM co-optimization

V. Iyengar, K. Chakrabarty, E.J. Marinissen

Research output: Chapter in Book/Report/Conference proceedingChapterAcademicpeer-review

140 Citations (Scopus)

Abstract

The testing time for a system-on-chip (SOC) is determined to a large extent by the design of test wrappers and the test access mechanism (TAM). Wrapper/TAM co-optimization is therefore necessary for minimizing SOC testing time. We recently proposed an exact technique for co-optimization based on a combination of integer linear programming (ILP) and exhaustive enumeration. However, this approach is computationally expensive for large SOCs, and it is limited to fixed-width test buses. We present a new approach for wrapper/TAM co-optimization based on generalized rectangle packing, also referred to as two-dimensional packing. This approach allows us to decrease testing time by reducing the mismatch between a core's test data needs and the width of the TAM to which it is assigned. We apply our co-optimization technique to an academic benchmark SOC and three industrial SOCs. Compared to the ILP-based technique, we obtain lower or comparable testing times for two out of the three industrial SOCs. Moreover, we obtain more than two orders of magnitude decrease in the CPU time needed for wrapper/TAM co-design.
Original languageEnglish
Title of host publicationProceedings 20th IEEE VLSI Test Symposium (VTS 2002)
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages253-258
ISBN (Print)0-7695-1570-3
DOIs
Publication statusPublished - 2002
Externally publishedYes

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