Abstract
Read and write assist techniques are widely adopted to allow voltage scaling in low-power SRAMs. In particular, this paper analyzes two assist techniques: word line level reduction and negative bit line boost. The analyzed assist techniques improve read stability and write margin of core-cells when the SRAM operates at a lowered supply voltage. In this work, we investigate the impact of such assist techniques on the faulty behavior of low-power SRAMs. This analysis is based on extensive injection of resistive-open and resistive-bridging defects in core-cells of a commercial low-power SRAM. Our study determines the most stressful configuration of assist circuits to detect each faulty behavior induced by injected defects. We show that, by applying most stressful configurations of assist circuits during test phase, defect coverage can be increased up to 89% w.r.t. test solutions that do not exploit assist circuits. Based on this analysis, we present an efficient test solution that exploits the configuration of assist circuits as a parameter to maximize the detection of studied defects, while reducing time complexity up to 73% w.r.t. test flows using state-of-the-art test algorithms.
Original language | English |
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Title of host publication | 2013 IEEE International Test Conference (ITC) |
Publisher | Institute of Electrical and Electronics Engineers |
Number of pages | 10 |
ISBN (Electronic) | 978-1-4799-0859-2 |
DOIs | |
Publication status | Published - 4 Nov 2013 |
Externally published | Yes |
Event | 2013 IEEE International Test Conference (ITC) - Anaheim, United States Duration: 6 Sept 2013 → 13 Sept 2013 |
Conference
Conference | 2013 IEEE International Test Conference (ITC) |
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Country/Territory | United States |
City | Anaheim |
Period | 6/09/13 → 13/09/13 |