On the Performance Exploration of 3D NoCs with Resistive-Open TSVs

Charles Effiong, Vianney Lapotre, Abdoulaye Gamatié, Gilles Sassatelli, Aida Todri-Sanial, Khalid Latif

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Abstract

Three-dimensional Networks-on-Chip (3D NoCs) are based on Through-Silicon-Vias (TSV), which offer several advantages such as stacking, high throughput and energy efficiency. However, TSVs suffer from design process variations. On the other hand, designing purely asynchronous serializers enables reliable inter-tier communication with moderate performance overhead. A side benefit lies in the intrinsic delay insensitivity of asynchronous logic which exploits serialized TSV links to their full timing potential, thereby mitigating process variability impact. This paper explores similar impact on 3D NoCs. It considers randomly generated process variation maps for which the impact on performance is analyzed according to various design parameters, e.g. TSV probabilistic delay distributions, TSV size and serialization rate.
Original languageEnglish
Title of host publication2015 IEEE Computer Society Annual Symposium on VLSI
PublisherInstitute of Electrical and Electronics Engineers
Pages579-584
Number of pages6
ISBN (Electronic)978-1-4799-8719-1
DOIs
Publication statusPublished - 2015
Externally publishedYes
Event2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2015) - Montpellier, France
Duration: 8 Jul 201510 Jul 2015

Conference

Conference2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2015)
Country/TerritoryFrance
CityMontpellier
Period8/07/1510/07/15

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