On the Performance Exploration of 3D NoCs with Resistive-Open TSVs

Charles Effiong; Vianney Lapotre; Abdoulaye Gamatié; Gilles Sassatelli; Aida Todri-Sanial; Khalid Latif

doi:10.1109/ISVLSI.2015.49

On the Performance Exploration of 3D NoCs with Resistive-Open TSVs

Charles Effiong, Vianney Lapotre, Abdoulaye Gamatié, Gilles Sassatelli, Aida Todri-Sanial, Khalid Latif

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Abstract

Three-dimensional Networks-on-Chip (3D NoCs) are based on Through-Silicon-Vias (TSV), which offer several advantages such as stacking, high throughput and energy efficiency. However, TSVs suffer from design process variations. On the other hand, designing purely asynchronous serializers enables reliable inter-tier communication with moderate performance overhead. A side benefit lies in the intrinsic delay insensitivity of asynchronous logic which exploits serialized TSV links to their full timing potential, thereby mitigating process variability impact. This paper explores similar impact on 3D NoCs. It considers randomly generated process variation maps for which the impact on performance is analyzed according to various design parameters, e.g. TSV probabilistic delay distributions, TSV size and serialization rate.

Original language	English
Title of host publication	2015 IEEE Computer Society Annual Symposium on VLSI
Publisher	Institute of Electrical and Electronics Engineers
Pages	579-584
Number of pages	6
ISBN (Electronic)	978-1-4799-8719-1
DOIs	https://doi.org/10.1109/ISVLSI.2015.49
Publication status	Published - 2015
Externally published	Yes
Event	2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2015) - Montpellier, France Duration: 8 Jul 2015 → 10 Jul 2015

Conference

Conference	2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2015)
Country/Territory	France
City	Montpellier
Period	8/07/15 → 10/07/15

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/ISVLSI.2015.49

Cite this

@inproceedings{946d00813a36479ab0dd399fa2b90bae,

title = "On the Performance Exploration of 3D NoCs with Resistive-Open TSVs",

abstract = "Three-dimensional Networks-on-Chip (3D NoCs) are based on Through-Silicon-Vias (TSV), which offer several advantages such as stacking, high throughput and energy efficiency. However, TSVs suffer from design process variations. On the other hand, designing purely asynchronous serializers enables reliable inter-tier communication with moderate performance overhead. A side benefit lies in the intrinsic delay insensitivity of asynchronous logic which exploits serialized TSV links to their full timing potential, thereby mitigating process variability impact. This paper explores similar impact on 3D NoCs. It considers randomly generated process variation maps for which the impact on performance is analyzed according to various design parameters, e.g. TSV probabilistic delay distributions, TSV size and serialization rate.",

author = "Charles Effiong and Vianney Lapotre and Abdoulaye Gamati{\'e} and Gilles Sassatelli and Aida Todri-Sanial and Khalid Latif",

year = "2015",

doi = "10.1109/ISVLSI.2015.49",

language = "English",

pages = "579--584",

booktitle = "2015 IEEE Computer Society Annual Symposium on VLSI",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2015) ; Conference date: 08-07-2015 Through 10-07-2015",

}

Effiong, C, Lapotre, V, Gamatié, A, Sassatelli, G, Todri-Sanial, A & Latif, K 2015, On the Performance Exploration of 3D NoCs with Resistive-Open TSVs. in 2015 IEEE Computer Society Annual Symposium on VLSI. Institute of Electrical and Electronics Engineers, pp. 579-584, 2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2015), Montpellier, France, 8/07/15. https://doi.org/10.1109/ISVLSI.2015.49

On the Performance Exploration of 3D NoCs with Resistive-Open TSVs. / Effiong, Charles; Lapotre, Vianney; Gamatié, Abdoulaye et al.
2015 IEEE Computer Society Annual Symposium on VLSI. Institute of Electrical and Electronics Engineers, 2015. p. 579-584.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - On the Performance Exploration of 3D NoCs with Resistive-Open TSVs

AU - Effiong, Charles

AU - Lapotre, Vianney

AU - Gamatié, Abdoulaye

AU - Sassatelli, Gilles

AU - Todri-Sanial, Aida

AU - Latif, Khalid

PY - 2015

Y1 - 2015

N2 - Three-dimensional Networks-on-Chip (3D NoCs) are based on Through-Silicon-Vias (TSV), which offer several advantages such as stacking, high throughput and energy efficiency. However, TSVs suffer from design process variations. On the other hand, designing purely asynchronous serializers enables reliable inter-tier communication with moderate performance overhead. A side benefit lies in the intrinsic delay insensitivity of asynchronous logic which exploits serialized TSV links to their full timing potential, thereby mitigating process variability impact. This paper explores similar impact on 3D NoCs. It considers randomly generated process variation maps for which the impact on performance is analyzed according to various design parameters, e.g. TSV probabilistic delay distributions, TSV size and serialization rate.

AB - Three-dimensional Networks-on-Chip (3D NoCs) are based on Through-Silicon-Vias (TSV), which offer several advantages such as stacking, high throughput and energy efficiency. However, TSVs suffer from design process variations. On the other hand, designing purely asynchronous serializers enables reliable inter-tier communication with moderate performance overhead. A side benefit lies in the intrinsic delay insensitivity of asynchronous logic which exploits serialized TSV links to their full timing potential, thereby mitigating process variability impact. This paper explores similar impact on 3D NoCs. It considers randomly generated process variation maps for which the impact on performance is analyzed according to various design parameters, e.g. TSV probabilistic delay distributions, TSV size and serialization rate.

U2 - 10.1109/ISVLSI.2015.49

DO - 10.1109/ISVLSI.2015.49

M3 - Conference contribution

SP - 579

EP - 584

BT - 2015 IEEE Computer Society Annual Symposium on VLSI

PB - Institute of Electrical and Electronics Engineers

T2 - 2015 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2015)

Y2 - 8 July 2015 through 10 July 2015

ER -

On the Performance Exploration of 3D NoCs with Resistive-Open TSVs

Abstract

Conference

UN SDGs

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