On the design of multimedia software and future system architectures

P.H.N. With, de, Egbert Jaspers

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A principal challenge for reducing the cost for designing complex systems-on-chip is to pursue more generic systems for a broad range of products. For this purpose, we explore three new architectural concepts for state-of-art video applications. First, we discuss a reusable scalable hardware architecture employing a hierarchical communication network fitting with the natural hierarchy of the application. In a case study, we show that MPEG streaming in DTV occurs at high level, while subsystems communicate at lower levels. The second concept is a software design that scales over a number of processors to enable reuse over a range of VLSI process technologies. We explore this via an H.264 decoder implementation scaling nearly linearly over up to eight processors by applying data partitioning. The third topic is resource-scalability, which is required to satisfy realtime constraints in a system with a high amount of shared resources. An example complexity-scalable MPEG-2 coder scales the required cycle budget with a factor of three, in parallel with a smooth degradation of quality.
Original languageEnglish
Title of host publicationElectronic Imaging 2004, Embedded Processors for Multimedia and Communications
EditorsS.I. Sudharsanan, M. Bove, S. Panchanathan
Place of PublicationBellingham, USA
ISBN (Print)0-8194-5212-2
Publication statusPublished - 2004

Publication series

NameProceedings of SPIE
ISSN (Print)0277-786X


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