On-chip toggle generators to provide realistic conditions during test of digital 2D-SoCs and 3D-SICs

Leonidas Katselas; Alkis Hatzopoulos; Hailong Jiao; Christos Papameletis; Erik Jan Marinissen

doi:10.1109/TEST.2018.8624803

On-chip toggle generators to provide realistic conditions during test of digital 2D-SoCs and 3D-SICs

Leonidas Katselas, Alkis Hatzopoulos, Hailong Jiao, Christos Papameletis, Erik Jan Marinissen

Electronic Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

3 Citations (Scopus)

Abstract

In digital logic circuits, unconstrained scan tests are known to evoke much higher switching activity than functional modes. State-of-the-art ATPG tools have knobs to constrain the switching activity of the generated test to a user-defined functional level. Two-dimensional System-on-Chips (2D-SoCs) and three-dimensional stacked ICs (3D-SICs) are typically tested in a modular fashion, i.e., per embedded core or stacked die. At any moment during the test, one or more modules are tested ('module-under-test', MUT). In this work, we present the impact of the switching activity in the currently not-tested modules (which we refer to as 'neighbors' of the MUT) on overall IR-drop and propose a method to provide realistic conditions during modular test of digital 2D-SoCs and 3D-SICs, using on-chip programmable toggle generators.

Original language	English
Title of host publication	International Test Conference 2018, ITC 2018 - Proceedings
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Number of pages	9
ISBN (Electronic)	978-1-5386-8382-8
ISBN (Print)	978-1-5386-8383-5
DOIs	https://doi.org/10.1109/TEST.2018.8624803
Publication status	Published - 30 Oct 2018
Event	49th IEEE International Test Conference, ITC 2018 - Phoenix, United States Duration: 29 Oct 2018 → 1 Nov 2018

Conference

Conference	49th IEEE International Test Conference, ITC 2018
Country/Territory	United States
City	Phoenix
Period	29/10/18 → 1/11/18

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10.1109/TEST.2018.8624803

Cite this

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title = "On-chip toggle generators to provide realistic conditions during test of digital 2D-SoCs and 3D-SICs",

abstract = "In digital logic circuits, unconstrained scan tests are known to evoke much higher switching activity than functional modes. State-of-the-art ATPG tools have knobs to constrain the switching activity of the generated test to a user-defined functional level. Two-dimensional System-on-Chips (2D-SoCs) and three-dimensional stacked ICs (3D-SICs) are typically tested in a modular fashion, i.e., per embedded core or stacked die. At any moment during the test, one or more modules are tested ('module-under-test', MUT). In this work, we present the impact of the switching activity in the currently not-tested modules (which we refer to as 'neighbors' of the MUT) on overall IR-drop and propose a method to provide realistic conditions during modular test of digital 2D-SoCs and 3D-SICs, using on-chip programmable toggle generators.",

author = "Leonidas Katselas and Alkis Hatzopoulos and Hailong Jiao and Christos Papameletis and Marinissen, \{Erik Jan\}",

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booktitle = "International Test Conference 2018, ITC 2018 - Proceedings",

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note = "49th IEEE International Test Conference, ITC 2018 ; Conference date: 29-10-2018 Through 01-11-2018",

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Katselas, L, Hatzopoulos, A, Jiao, H, Papameletis, C & Marinissen, EJ 2018, On-chip toggle generators to provide realistic conditions during test of digital 2D-SoCs and 3D-SICs. in International Test Conference 2018, ITC 2018 - Proceedings., 8624803, Institute of Electrical and Electronics Engineers, Piscataway, 49th IEEE International Test Conference, ITC 2018, Phoenix, United States, 29/10/18. https://doi.org/10.1109/TEST.2018.8624803

On-chip toggle generators to provide realistic conditions during test of digital 2D-SoCs and 3D-SICs. / Katselas, Leonidas; Hatzopoulos, Alkis; Jiao, Hailong et al.
International Test Conference 2018, ITC 2018 - Proceedings. Piscataway: Institute of Electrical and Electronics Engineers, 2018. 8624803.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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T1 - On-chip toggle generators to provide realistic conditions during test of digital 2D-SoCs and 3D-SICs

AU - Katselas, Leonidas

AU - Hatzopoulos, Alkis

AU - Jiao, Hailong

AU - Papameletis, Christos

AU - Marinissen, Erik Jan

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N2 - In digital logic circuits, unconstrained scan tests are known to evoke much higher switching activity than functional modes. State-of-the-art ATPG tools have knobs to constrain the switching activity of the generated test to a user-defined functional level. Two-dimensional System-on-Chips (2D-SoCs) and three-dimensional stacked ICs (3D-SICs) are typically tested in a modular fashion, i.e., per embedded core or stacked die. At any moment during the test, one or more modules are tested ('module-under-test', MUT). In this work, we present the impact of the switching activity in the currently not-tested modules (which we refer to as 'neighbors' of the MUT) on overall IR-drop and propose a method to provide realistic conditions during modular test of digital 2D-SoCs and 3D-SICs, using on-chip programmable toggle generators.

AB - In digital logic circuits, unconstrained scan tests are known to evoke much higher switching activity than functional modes. State-of-the-art ATPG tools have knobs to constrain the switching activity of the generated test to a user-defined functional level. Two-dimensional System-on-Chips (2D-SoCs) and three-dimensional stacked ICs (3D-SICs) are typically tested in a modular fashion, i.e., per embedded core or stacked die. At any moment during the test, one or more modules are tested ('module-under-test', MUT). In this work, we present the impact of the switching activity in the currently not-tested modules (which we refer to as 'neighbors' of the MUT) on overall IR-drop and propose a method to provide realistic conditions during modular test of digital 2D-SoCs and 3D-SICs, using on-chip programmable toggle generators.

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M3 - Conference contribution

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BT - International Test Conference 2018, ITC 2018 - Proceedings

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ER -

On-chip toggle generators to provide realistic conditions during test of digital 2D-SoCs and 3D-SICs

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