Abstract
Simulation of the influence of interconnect structures and substrates is essential for a good understanding of modern chip behavior. Sometimes such simulations are not feasible with current circuit simulators. We propose an approach to reduce the large resistor networks obtained from extraction of the parasitic effects that builds upon the work in (Rommes and Schilders, IEEE Trans. CAD Circ. Syst. 29:28–39, 2010). The novelty in our approach is that we obtain improved reductions, by developing error estimations which enable to delete superfluous resistors and to control accuracy. An industrial test case demonstrates the potential of the new method.
Original language | English |
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Title of host publication | Proceedings of the 8th Conference on Scientific Computing in Electrical Engineering (SCEE 2010, Toulouse, France, September 19-24, 2012) |
Editors | B. Michielsen, J.R. Poirier |
Place of Publication | Berlin |
Publisher | Springer |
Pages | 377-385 |
ISBN (Print) | 978-3-642-22452-2 |
DOIs | |
Publication status | Published - 2012 |
Event | Scientific Computing in Electrical Engineering, SCEE 2010 - Toulouse, France Duration: 19 Sep 2010 → 24 Sep 2010 https://scee-conferences.org/ |
Publication series
Name | Mathematics in Industry |
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Volume | 16 |
ISSN (Print) | 1612-3956 |
Conference
Conference | Scientific Computing in Electrical Engineering, SCEE 2010 |
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Country/Territory | France |
City | Toulouse |
Period | 19/09/10 → 24/09/10 |
Other | SCEE 2010 |
Internet address |