On approximate reduction of multi-port resistor networks

M. Ugryumova, J. Rommes, W.H.A. Schilders

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Abstract

Simulation of the influence of interconnect structures and substrates is essential for a good understanding of modern chip behavior. Sometimes such simulations are not feasible with current circuit simulators. We propose an approach to reduce the large resistor networks obtained from extraction of the parasitic effects that builds upon the work in (Rommes and Schilders, IEEE Trans. CAD Circ. Syst. 29:28–39, 2010). The novelty in our approach is that we obtain improved reductions, by developing error estimations which enable to delete superfluous resistors and to control accuracy. An industrial test case demonstrates the potential of the new method.
Original languageEnglish
Title of host publicationProceedings of the 8th Conference on Scientific Computing in Electrical Engineering (SCEE 2010, Toulouse, France, September 19-24, 2012)
EditorsB. Michielsen, J.R. Poirier
Place of PublicationBerlin
PublisherSpringer
Pages377-385
ISBN (Print)978-3-642-22452-2
DOIs
Publication statusPublished - 2012
Eventconference; SCEE 2010; 2010-09-19; 2010-09-24 -
Duration: 19 Sep 201024 Sep 2010

Publication series

NameMathematics in Industry
Volume16
ISSN (Print)1612-3956

Conference

Conferenceconference; SCEE 2010; 2010-09-19; 2010-09-24
Period19/09/1024/09/10
OtherSCEE 2010

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