Abstract
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the 8th Conference on Scientific Computing in Electrical Engineering (SCEE 2010, Toulouse, France, September 19-24, 2012) |
| Editors | B. Michielsen, J.R. Poirier |
| Place of Publication | Berlin |
| Publisher | Springer |
| Pages | 377-385 |
| ISBN (Print) | 978-3-642-22452-2 |
| DOIs | |
| Publication status | Published - 2012 |
| Event | conference; SCEE 2010; 2010-09-19; 2010-09-24 - Duration: 19 Sep 2010 → 24 Sep 2010 |
Publication series
| Name | Mathematics in Industry |
|---|---|
| Volume | 16 |
| ISSN (Print) | 1612-3956 |
Conference
| Conference | conference; SCEE 2010; 2010-09-19; 2010-09-24 |
|---|---|
| Period | 19/09/10 → 24/09/10 |
| Other | SCEE 2010 |
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On approximate reduction of multi-port resistor networks. / Ugryumova, M.; Rommes, J.; Schilders, W.H.A.
Proceedings of the 8th Conference on Scientific Computing in Electrical Engineering (SCEE 2010, Toulouse, France, September 19-24, 2012). ed. / B. Michielsen; J.R. Poirier. Berlin : Springer, 2012. p. 377-385 (Mathematics in Industry; Vol. 16).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
TY - GEN
T1 - On approximate reduction of multi-port resistor networks
AU - Ugryumova, M.
AU - Rommes, J.
AU - Schilders, W.H.A.
PY - 2012
Y1 - 2012
N2 - Simulation of the influence of interconnect structures and substrates is essential for a good understanding of modern chip behavior. Sometimes such simulations are not feasible with current circuit simulators. We propose an approach to reduce the large resistor networks obtained from extraction of the parasitic effects that builds upon the work in (Rommes and Schilders, IEEE Trans. CAD Circ. Syst. 29:28–39, 2010). The novelty in our approach is that we obtain improved reductions, by developing error estimations which enable to delete superfluous resistors and to control accuracy. An industrial test case demonstrates the potential of the new method.
AB - Simulation of the influence of interconnect structures and substrates is essential for a good understanding of modern chip behavior. Sometimes such simulations are not feasible with current circuit simulators. We propose an approach to reduce the large resistor networks obtained from extraction of the parasitic effects that builds upon the work in (Rommes and Schilders, IEEE Trans. CAD Circ. Syst. 29:28–39, 2010). The novelty in our approach is that we obtain improved reductions, by developing error estimations which enable to delete superfluous resistors and to control accuracy. An industrial test case demonstrates the potential of the new method.
U2 - 10.1007/978-3-642-22453-9_40
DO - 10.1007/978-3-642-22453-9_40
M3 - Conference contribution
SN - 978-3-642-22452-2
T3 - Mathematics in Industry
SP - 377
EP - 385
BT - Proceedings of the 8th Conference on Scientific Computing in Electrical Engineering (SCEE 2010, Toulouse, France, September 19-24, 2012)
A2 - Michielsen, B.
A2 - Poirier, J.R.
PB - Springer
CY - Berlin
ER -