On approximate reduction of multi-port resistor networks

M. Ugryumova; J. Rommes; W.H.A. Schilders

doi:10.1007/978-3-642-22453-9_40

On approximate reduction of multi-port resistor networks

M. Ugryumova, J. Rommes, W.H.A. Schilders

Scientific Computing

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Abstract

Simulation of the influence of interconnect structures and substrates is essential for a good understanding of modern chip behavior. Sometimes such simulations are not feasible with current circuit simulators. We propose an approach to reduce the large resistor networks obtained from extraction of the parasitic effects that builds upon the work in (Rommes and Schilders, IEEE Trans. CAD Circ. Syst. 29:28–39, 2010). The novelty in our approach is that we obtain improved reductions, by developing error estimations which enable to delete superfluous resistors and to control accuracy. An industrial test case demonstrates the potential of the new method.

Original language	English
Title of host publication	Proceedings of the 8th Conference on Scientific Computing in Electrical Engineering (SCEE 2010, Toulouse, France, September 19-24, 2012)
Editors	B. Michielsen, J.R. Poirier
Place of Publication	Berlin
Publisher	Springer
Pages	377-385
ISBN (Print)	978-3-642-22452-2
DOIs	https://doi.org/10.1007/978-3-642-22453-9_40
Publication status	Published - 2012
Event	Scientific Computing in Electrical Engineering, SCEE 2010 - Toulouse, France Duration: 19 Sep 2010 → 24 Sep 2010 https://scee-conferences.org/

Publication series

Name	Mathematics in Industry
Volume	16
ISSN (Print)	1612-3956

Conference

Conference	Scientific Computing in Electrical Engineering, SCEE 2010
Country/Territory	France
City	Toulouse
Period	19/09/10 → 24/09/10
Other	SCEE 2010
Internet address	https://scee-conferences.org/

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10.1007/978-3-642-22453-9_40

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Ugryumova, M., Rommes, J., & Schilders, W. H. A. (2012). On approximate reduction of multi-port resistor networks. In B. Michielsen, & J. R. Poirier (Eds.), Proceedings of the 8th Conference on Scientific Computing in Electrical Engineering (SCEE 2010, Toulouse, France, September 19-24, 2012) (pp. 377-385). (Mathematics in Industry; Vol. 16). Springer. https://doi.org/10.1007/978-3-642-22453-9_40

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title = "On approximate reduction of multi-port resistor networks",

abstract = "Simulation of the influence of interconnect structures and substrates is essential for a good understanding of modern chip behavior. Sometimes such simulations are not feasible with current circuit simulators. We propose an approach to reduce the large resistor networks obtained from extraction of the parasitic effects that builds upon the work in (Rommes and Schilders, IEEE Trans. CAD Circ. Syst. 29:28–39, 2010). The novelty in our approach is that we obtain improved reductions, by developing error estimations which enable to delete superfluous resistors and to control accuracy. An industrial test case demonstrates the potential of the new method.",

author = "M. Ugryumova and J. Rommes and W.H.A. Schilders",

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Ugryumova, M, Rommes, J & Schilders, WHA 2012, On approximate reduction of multi-port resistor networks. in B Michielsen & JR Poirier (eds), Proceedings of the 8th Conference on Scientific Computing in Electrical Engineering (SCEE 2010, Toulouse, France, September 19-24, 2012). Mathematics in Industry, vol. 16, Springer, Berlin, pp. 377-385, Scientific Computing in Electrical Engineering, SCEE 2010, Toulouse, France, 19/09/10. https://doi.org/10.1007/978-3-642-22453-9_40

On approximate reduction of multi-port resistor networks. / Ugryumova, M.; Rommes, J.; Schilders, W.H.A.

Proceedings of the 8th Conference on Scientific Computing in Electrical Engineering (SCEE 2010, Toulouse, France, September 19-24, 2012). ed. / B. Michielsen; J.R. Poirier. Berlin : Springer, 2012. p. 377-385 (Mathematics in Industry; Vol. 16).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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N2 - Simulation of the influence of interconnect structures and substrates is essential for a good understanding of modern chip behavior. Sometimes such simulations are not feasible with current circuit simulators. We propose an approach to reduce the large resistor networks obtained from extraction of the parasitic effects that builds upon the work in (Rommes and Schilders, IEEE Trans. CAD Circ. Syst. 29:28–39, 2010). The novelty in our approach is that we obtain improved reductions, by developing error estimations which enable to delete superfluous resistors and to control accuracy. An industrial test case demonstrates the potential of the new method.

AB - Simulation of the influence of interconnect structures and substrates is essential for a good understanding of modern chip behavior. Sometimes such simulations are not feasible with current circuit simulators. We propose an approach to reduce the large resistor networks obtained from extraction of the parasitic effects that builds upon the work in (Rommes and Schilders, IEEE Trans. CAD Circ. Syst. 29:28–39, 2010). The novelty in our approach is that we obtain improved reductions, by developing error estimations which enable to delete superfluous resistors and to control accuracy. An industrial test case demonstrates the potential of the new method.

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T2 - Scientific Computing in Electrical Engineering, SCEE 2010

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On approximate reduction of multi-port resistor networks

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