Simulation of the influence of interconnect structures and substrates is essential for a good understanding of modern chip behavior. Sometimes such simulations are not feasible with current circuit simulators. We propose an approach to reduce the large resistor networks obtained from extraction of the parasitic effects that builds upon the work in (Rommes and Schilders, IEEE Trans. CAD Circ. Syst. 29:28–39, 2010). The novelty in our approach is that we obtain improved reductions, by developing error estimations which enable to delete superfluous resistors and to control accuracy. An industrial test case demonstrates the potential of the new method.
|Name||Mathematics in Industry|
|Conference||conference; SCEE 2010; 2010-09-19; 2010-09-24|
|Period||19/09/10 → 24/09/10|