Abstract
Convolutional neural networks (CNNs) have become the dominant neural network architecture for solving many state-of-the-art (SOA) visual processing tasks. Even though graphical processing units are most often used in training and deploying CNNs, their power efficiency is less than 10 GOp/s/W for single-frame runtime inference. We propose a flexible and efficient CNN accelerator architecture called NullHop that implements SOA CNNs useful for low-power and low-latency application scenarios. NullHop exploits the sparsity of neuron activations in CNNs to accelerate the computation and reduce memory requirements. The flexible architecture allows high utilization of available computing resources across kernel sizes ranging from 1 × 1 to 7 × 7. NullHop can process up to 128 input and 128 output feature maps per layer in a single pass. We implemented the proposed architecture on a Xilinx Zynq field-programmable gate array (FPGA) platform and presented the results showing how our implementation reduces external memory transfers and compute time in five different CNNs ranging from small ones up to the widely known large VGG16 and VGG19 CNNs. Postsynthesis simulations using Mentor Modelsim in a 28-nm process with a clock frequency of 500 MHz show that the VGG19 network achieves over 450 GOp/s. By exploiting sparsity, NullHop achieves an efficiency of 368%, maintains over 98% utilization of the multiply-accumulate units, and achieves a power efficiency of over 3 TOp/s/W in a core area of 6.3 mm 2 . As further proof of NullHop's usability, we interfaced its FPGA implementation with a neuromorphic event camera for real-time interactive demonstrations.
Original language | English |
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Article number | 8421093 |
Pages (from-to) | 644-656 |
Number of pages | 13 |
Journal | IEEE Transactions on Neural Networks and Learning Systems |
Volume | 30 |
Issue number | 3 |
DOIs | |
Publication status | Published - 1 Mar 2019 |
Externally published | Yes |
Bibliographical note
Funding Information:Manuscript received May 31, 2017; revised November 24, 2017 and March 6, 2018; accepted June 22, 2018. Date of publication July 26, 2018; date of current version February 19, 2019. This work was supported by the Samsung Advanced Institute of Technology, University of Zurich and ETH Zurich. (Corresponding author: Alessandro Aimar.) A. Aimar, E. Calabrese, I.-A. Lungu, M. B. Milde, S.-C. Liu, and T. Delbruck are with the Institute of Neuroinformatics, University of Zurich and ETH Zurich, 8057 Zürich, Switzerland (e-mail: alessandro.aimar@ ini.uzh.ch).
Publisher Copyright:
© 2012 IEEE.
Funding
Manuscript received May 31, 2017; revised November 24, 2017 and March 6, 2018; accepted June 22, 2018. Date of publication July 26, 2018; date of current version February 19, 2019. This work was supported by the Samsung Advanced Institute of Technology, University of Zurich and ETH Zurich. (Corresponding author: Alessandro Aimar.) A. Aimar, E. Calabrese, I.-A. Lungu, M. B. Milde, S.-C. Liu, and T. Delbruck are with the Institute of Neuroinformatics, University of Zurich and ETH Zurich, 8057 Zürich, Switzerland (e-mail: alessandro.aimar@ ini.uzh.ch).
Keywords
- Artificial intelligence
- computer vision
- convolutional neural networks (CNNs)
- field-programmable gate array (FPGA)
- VLSI