Novel approaches for low-cost through-silicon vias

J. E. Bullema, P. M.M.C. Bressers, G. Oosterhuis, M. Mueller, A. J. Huis in 't Veld, F. Roozeboom

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review


3D stacking of integrated circuits is an emerging packaging technology to enable a high degree of functional integration and miniaturization. Footprint reduction in 3D stacking can be achieved by use of Through Silicon Vias (TSV). Creation of TSVs with Deep Reactive Ion Etching (DRIE), laser drilling and pulse reverse plating is established technology. Current TSV technologies are considered as high cost processes due to expensive equipment and long processing times. In this paper three novel technological approaches to create TSVs are described that potentially lead to a creation of low-cost Through Silicon Vias. The technologies in development discussed here, were identified based upon cost of ownership analysis of current TSV creation processes The paper presents the first results of the different approaches.

Original languageEnglish
Title of host publicationEMPC-2011 - 18th European Microelectronics and Packaging Conference, Proceedings
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Number of pages5
ISBN (Print)9780956808608
Publication statusPublished - 1 Dec 2011
Event18th European Microelectronics and Packaging Conference (EMPC-2011) - Brighton, United Kingdom
Duration: 12 Sept 201115 Sept 2011


Conference18th European Microelectronics and Packaging Conference (EMPC-2011)
Country/TerritoryUnited Kingdom


  • Deep Reactive Ion etching
  • Electrochemical Machining
  • Laser Induced Forward Transfer
  • Through Silicon Via


Dive into the research topics of 'Novel approaches for low-cost through-silicon vias'. Together they form a unique fingerprint.

Cite this