Novel approaches for low-cost through-silicon vias

J. E. Bullema; P. M.M.C. Bressers; G. Oosterhuis; M. Mueller; A. J. Huis in 't Veld; F. Roozeboom

Novel approaches for low-cost through-silicon vias

J. E. Bullema, P. M.M.C. Bressers, G. Oosterhuis, M. Mueller, A. J. Huis in 't Veld, F. Roozeboom

Plasma & Materials Processing

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Abstract

3D stacking of integrated circuits is an emerging packaging technology to enable a high degree of functional integration and miniaturization. Footprint reduction in 3D stacking can be achieved by use of Through Silicon Vias (TSV). Creation of TSVs with Deep Reactive Ion Etching (DRIE), laser drilling and pulse reverse plating is established technology. Current TSV technologies are considered as high cost processes due to expensive equipment and long processing times. In this paper three novel technological approaches to create TSVs are described that potentially lead to a creation of low-cost Through Silicon Vias. The technologies in development discussed here, were identified based upon cost of ownership analysis of current TSV creation processes The paper presents the first results of the different approaches.

Original language	English
Title of host publication	EMPC-2011 - 18th European Microelectronics and Packaging Conference, Proceedings
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Number of pages	5
ISBN (Print)	9780956808608
Publication status	Published - 1 Dec 2011
Event	18th European Microelectronics and Packaging Conference (EMPC-2011) - Brighton, United Kingdom Duration: 12 Sep 2011 → 15 Sep 2011

Conference

Conference	18th European Microelectronics and Packaging Conference (EMPC-2011)
Country/Territory	United Kingdom
City	Brighton
Period	12/09/11 → 15/09/11

Keywords

Deep Reactive Ion etching
Electrochemical Machining
Laser Induced Forward Transfer
Through Silicon Via

Cite this

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title = "Novel approaches for low-cost through-silicon vias",

abstract = "3D stacking of integrated circuits is an emerging packaging technology to enable a high degree of functional integration and miniaturization. Footprint reduction in 3D stacking can be achieved by use of Through Silicon Vias (TSV). Creation of TSVs with Deep Reactive Ion Etching (DRIE), laser drilling and pulse reverse plating is established technology. Current TSV technologies are considered as high cost processes due to expensive equipment and long processing times. In this paper three novel technological approaches to create TSVs are described that potentially lead to a creation of low-cost Through Silicon Vias. The technologies in development discussed here, were identified based upon cost of ownership analysis of current TSV creation processes The paper presents the first results of the different approaches.",

keywords = "Deep Reactive Ion etching, Electrochemical Machining, Laser Induced Forward Transfer, Through Silicon Via",

author = "Bullema, {J. E.} and Bressers, {P. M.M.C.} and G. Oosterhuis and M. Mueller and {Huis in 't Veld}, {A. J.} and F. Roozeboom",

year = "2011",

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booktitle = "EMPC-2011 - 18th European Microelectronics and Packaging Conference, Proceedings",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "18th European Microelectronics and Packaging Conference (EMPC-2011) ; Conference date: 12-09-2011 Through 15-09-2011",

}

Bullema, JE, Bressers, PMMC, Oosterhuis, G, Mueller, M, Huis in 't Veld, AJ & Roozeboom, F 2011, Novel approaches for low-cost through-silicon vias. in EMPC-2011 - 18th European Microelectronics and Packaging Conference, Proceedings., 6142399, Institute of Electrical and Electronics Engineers, Piscataway, 18th European Microelectronics and Packaging Conference (EMPC-2011), Brighton, United Kingdom, 12/09/11.

Novel approaches for low-cost through-silicon vias. / Bullema, J. E.; Bressers, P. M.M.C.; Oosterhuis, G.; Mueller, M.; Huis in 't Veld, A. J.; Roozeboom, F.

EMPC-2011 - 18th European Microelectronics and Packaging Conference, Proceedings. Piscataway : Institute of Electrical and Electronics Engineers, 2011. 6142399.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Novel approaches for low-cost through-silicon vias

AU - Bullema, J. E.

AU - Bressers, P. M.M.C.

AU - Oosterhuis, G.

AU - Mueller, M.

AU - Huis in 't Veld, A. J.

AU - Roozeboom, F.

PY - 2011/12/1

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N2 - 3D stacking of integrated circuits is an emerging packaging technology to enable a high degree of functional integration and miniaturization. Footprint reduction in 3D stacking can be achieved by use of Through Silicon Vias (TSV). Creation of TSVs with Deep Reactive Ion Etching (DRIE), laser drilling and pulse reverse plating is established technology. Current TSV technologies are considered as high cost processes due to expensive equipment and long processing times. In this paper three novel technological approaches to create TSVs are described that potentially lead to a creation of low-cost Through Silicon Vias. The technologies in development discussed here, were identified based upon cost of ownership analysis of current TSV creation processes The paper presents the first results of the different approaches.

AB - 3D stacking of integrated circuits is an emerging packaging technology to enable a high degree of functional integration and miniaturization. Footprint reduction in 3D stacking can be achieved by use of Through Silicon Vias (TSV). Creation of TSVs with Deep Reactive Ion Etching (DRIE), laser drilling and pulse reverse plating is established technology. Current TSV technologies are considered as high cost processes due to expensive equipment and long processing times. In this paper three novel technological approaches to create TSVs are described that potentially lead to a creation of low-cost Through Silicon Vias. The technologies in development discussed here, were identified based upon cost of ownership analysis of current TSV creation processes The paper presents the first results of the different approaches.

KW - Deep Reactive Ion etching

KW - Electrochemical Machining

KW - Laser Induced Forward Transfer

KW - Through Silicon Via

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BT - EMPC-2011 - 18th European Microelectronics and Packaging Conference, Proceedings

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T2 - 18th European Microelectronics and Packaging Conference (EMPC-2011)

Y2 - 12 September 2011 through 15 September 2011

ER -

Novel approaches for low-cost through-silicon vias

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Keywords

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