Noise reduction in nanometre CMOS

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Abstract

With nanometre scaling, the amount of transistors per 100 square millimetre will increase following Moore's Law. The maximum power will, without additional cooling, be limited to a few watt whereas the on- and off-chip clock and data speeds will increase further. To accommodate this, the core supply voltages are reduced further down to below 1 volt as where the peripheral supply voltages will have to follow international agreed voltages levels to enable interfacing. While lowering the core supply voltages, the on-chip noise margin will drop accordingly and tight on- and off-chip decoupling measures are necessary. However by application, RF switching noise from nanometre CMOS designs are forced out of their packages through the supply and ground pins when applying conventional off-chip decoupling is applied. In this paper, the state-of-the-art, as well as a new noise reduction technique, which is possible with today's nanometre CMOS processes, will be discussed together with guidance to accompanying complementary off-chip measures.
Original languageEnglish
Title of host publicationProceeding of APEMC 2010, April 12-16, Beijing, China
Pages1060-1063
DOIs
Publication statusPublished - 2010
Eventconference; Asia-Pacific Symposium on Electromagnetic Compatibility (APEMC 20100, April 12-16, Beijing, China - Beijing, China
Duration: 12 Apr 201016 Apr 2010

Conference

Conferenceconference; Asia-Pacific Symposium on Electromagnetic Compatibility (APEMC 20100, April 12-16, Beijing, China
Abbreviated titleAPEMC 2010
CountryChina
CityBeijing
Period12/04/1016/04/10
OtherAPEMC 2010, April 12-16, Beijing, China

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  • Cite this

    Coenen, M. J., & Roermund, van, A. H. M. (2010). Noise reduction in nanometre CMOS. In Proceeding of APEMC 2010, April 12-16, Beijing, China (pp. 1060-1063) https://doi.org/10.1109/APEMC.2010.5475539