Noise analysis of a BJT-based charge pump for low-noise PLL applications

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

2 Citations (Scopus)

Abstract

Noise of the charge pump degrades the in-band phase noise of charge pump phase-locked loop (CPPLL). This paper analyzes the noise mechanism of a bipolar junction transistor based charge pump and validates the analysis through simulation, providing necessary insight into the design of low-noise charge pump for CPPLL-based frequency synthesizers. A simple model for bipolar transistor noise is utilized to carry out the noise analysis. The scaling effects of the duty cycle and the rise/fall time of the input signals on the charge pump noise are also analyzed in detail. The analysis reveals that increased charge pump current reduces the PLL phase noise and that a trade-off exists between the area and the noise of the charge pump.
Original languageEnglish
Title of host publication2017 European Conference on Circuit Theory and Design (ECCTD), IEEE
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Number of pages4
ISBN (Electronic)978-1-5386-3974-0
DOIs
Publication statusPublished - Sep 2017
Event23rd European Conference on Circuit Theory and Design (ECCTD 2017), September 4-6, 2017, Catania, Italy - Catania, Italy
Duration: 4 Sep 20176 Sep 2017
http://www.ecctd2017.dieei.unict.it/

Conference

Conference23rd European Conference on Circuit Theory and Design (ECCTD 2017), September 4-6, 2017, Catania, Italy
Abbreviated titleECCTD 2017
CountryItaly
CityCatania
Period4/09/176/09/17
Internet address

Fingerprint

low noise
pumps
bipolar transistors
frequency synthesizers
junction transistors
scaling
cycles
simulation

Cite this

Dhar, D., van Zeijl, P. T. M., Milosevic, D., Gao, H., & Baltus, P. G. M. (2017). Noise analysis of a BJT-based charge pump for low-noise PLL applications. In 2017 European Conference on Circuit Theory and Design (ECCTD), IEEE [8093234] Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ECCTD.2017.8093234
Dhar, D. ; van Zeijl, P.T.M. ; Milosevic, D. ; Gao, H. ; Baltus, P.G.M. / Noise analysis of a BJT-based charge pump for low-noise PLL applications. 2017 European Conference on Circuit Theory and Design (ECCTD), IEEE. Piscataway : Institute of Electrical and Electronics Engineers, 2017.
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title = "Noise analysis of a BJT-based charge pump for low-noise PLL applications",
abstract = "Noise of the charge pump degrades the in-band phase noise of charge pump phase-locked loop (CPPLL). This paper analyzes the noise mechanism of a bipolar junction transistor based charge pump and validates the analysis through simulation, providing necessary insight into the design of low-noise charge pump for CPPLL-based frequency synthesizers. A simple model for bipolar transistor noise is utilized to carry out the noise analysis. The scaling effects of the duty cycle and the rise/fall time of the input signals on the charge pump noise are also analyzed in detail. The analysis reveals that increased charge pump current reduces the PLL phase noise and that a trade-off exists between the area and the noise of the charge pump.",
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Dhar, D, van Zeijl, PTM, Milosevic, D, Gao, H & Baltus, PGM 2017, Noise analysis of a BJT-based charge pump for low-noise PLL applications. in 2017 European Conference on Circuit Theory and Design (ECCTD), IEEE., 8093234, Institute of Electrical and Electronics Engineers, Piscataway, 23rd European Conference on Circuit Theory and Design (ECCTD 2017), September 4-6, 2017, Catania, Italy, Catania, Italy, 4/09/17. https://doi.org/10.1109/ECCTD.2017.8093234

Noise analysis of a BJT-based charge pump for low-noise PLL applications. / Dhar, D.; van Zeijl, P.T.M.; Milosevic, D.; Gao, H.; Baltus, P.G.M.

2017 European Conference on Circuit Theory and Design (ECCTD), IEEE. Piscataway : Institute of Electrical and Electronics Engineers, 2017. 8093234.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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AU - Baltus, P.G.M.

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N2 - Noise of the charge pump degrades the in-band phase noise of charge pump phase-locked loop (CPPLL). This paper analyzes the noise mechanism of a bipolar junction transistor based charge pump and validates the analysis through simulation, providing necessary insight into the design of low-noise charge pump for CPPLL-based frequency synthesizers. A simple model for bipolar transistor noise is utilized to carry out the noise analysis. The scaling effects of the duty cycle and the rise/fall time of the input signals on the charge pump noise are also analyzed in detail. The analysis reveals that increased charge pump current reduces the PLL phase noise and that a trade-off exists between the area and the noise of the charge pump.

AB - Noise of the charge pump degrades the in-band phase noise of charge pump phase-locked loop (CPPLL). This paper analyzes the noise mechanism of a bipolar junction transistor based charge pump and validates the analysis through simulation, providing necessary insight into the design of low-noise charge pump for CPPLL-based frequency synthesizers. A simple model for bipolar transistor noise is utilized to carry out the noise analysis. The scaling effects of the duty cycle and the rise/fall time of the input signals on the charge pump noise are also analyzed in detail. The analysis reveals that increased charge pump current reduces the PLL phase noise and that a trade-off exists between the area and the noise of the charge pump.

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Dhar D, van Zeijl PTM, Milosevic D, Gao H, Baltus PGM. Noise analysis of a BJT-based charge pump for low-noise PLL applications. In 2017 European Conference on Circuit Theory and Design (ECCTD), IEEE. Piscataway: Institute of Electrical and Electronics Engineers. 2017. 8093234 https://doi.org/10.1109/ECCTD.2017.8093234