NoC-based multiprocessor architecture for mixed-time-criticality applications

K.G.W. Goossens; M.L.P.J. Koedam; A.T. Nelson; S.S. Sinha; S. Goossens; Y. Li; G.D. Breaban; J.R. van Kampenhout; R. Tavakoli Najafabadi; J. Valencia; H. Ahmadi Balef; B. Akesson; S. Stuijk; M.C.W. Geilen; D. Goswami; M. Nabi Najafabadi

doi:10.1007/978-94-017-7267-9_17

NoC-based multiprocessor architecture for mixed-time-criticality applications

K.G.W. Goossens, M.L.P.J. Koedam, A.T. Nelson, S.S. Sinha, S. Goossens, Y. Li, G.D. Breaban, J.R. van Kampenhout, R. Tavakoli Najafabadi, J. Valencia, H. Ahmadi Balef, B. Akesson, S. Stuijk, M.C.W. Geilen, D. Goswami, M. Nabi Najafabadi

Research output: Chapter in Book/Report/Conference proceeding › Chapter › Academic › peer-review

13 Citations (Scopus)

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Abstract

In this chapter we define what a mixed-time-criticality system is and what its requirements are. After defining the concepts that such systems should follow, we described CompSOC, which is one example of a mixed-time-criticality platform. We describe, in detail, how multiple resources, such as processors, memories, and interconnect, are combined into a larger hardware platform, and especially how they are shared between applications using different arbitration schemes. Following this, the software architecture that transforms the single hardware platform into multiple virtual execution platforms, one per application, is described.

Original language	English
Title of host publication	Handbook of hardware/software codesign
Editors	S. Ha, J. Teich
Place of Publication	Dordrecht
Publisher	Springer
Pages	491-530
Number of pages	40
ISBN (Electronic)	978-94-017-7267-9
ISBN (Print)	978-94-017-7266-2
DOIs	https://doi.org/10.1007/978-94-017-7267-9_17
Publication status	Published - 1 Nov 2017

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Goossens, K. G. W., Koedam, M. L. P. J., Nelson, A. T., Sinha, S. S., Goossens, S., Li, Y., Breaban, G. D., van Kampenhout, J. R., Tavakoli Najafabadi, R., Valencia, J., Ahmadi Balef, H., Akesson, B., Stuijk, S., Geilen, M. C. W., Goswami, D., & Nabi Najafabadi, M. (2017). NoC-based multiprocessor architecture for mixed-time-criticality applications. In S. Ha, & J. Teich (Eds.), Handbook of hardware/software codesign (pp. 491-530). Springer. https://doi.org/10.1007/978-94-017-7267-9_17

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Goossens, KGW , Koedam, MLPJ , Nelson, AT, Sinha, SS, Goossens, S, Li, Y, Breaban, GD, van Kampenhout, JR, Tavakoli Najafabadi, R, Valencia, J, Ahmadi Balef, H, Akesson, B, Stuijk, S , Geilen, MCW , Goswami, D & Nabi Najafabadi, M 2017, NoC-based multiprocessor architecture for mixed-time-criticality applications. in S Ha & J Teich (eds), Handbook of hardware/software codesign. Springer, Dordrecht, pp. 491-530. https://doi.org/10.1007/978-94-017-7267-9_17

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AU - Sinha, S.S.

AU - Goossens, S.

AU - Li, Y.

AU - Breaban, G.D.

AU - van Kampenhout, J.R.

AU - Tavakoli Najafabadi, R.

AU - Valencia, J.

AU - Ahmadi Balef, H.

AU - Akesson, B.

AU - Stuijk, S.

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AB - In this chapter we define what a mixed-time-criticality system is and what its requirements are. After defining the concepts that such systems should follow, we described CompSOC, which is one example of a mixed-time-criticality platform. We describe, in detail, how multiple resources, such as processors, memories, and interconnect, are combined into a larger hardware platform, and especially how they are shared between applications using different arbitration schemes. Following this, the software architecture that transforms the single hardware platform into multiple virtual execution platforms, one per application, is described.

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NoC-based multiprocessor architecture for mixed-time-criticality applications

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