New AES software speed records

D.J. Bernstein, P. Schwabe

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

52 Citations (Scopus)
1 Downloads (Pure)

Abstract

This paper presents new speed records for AES software, taking advantage of (1) architecture-dependent reduction of instructions used to compute AES and (2) microarchitecture-dependent reduction of cycles used for those instructions. A wide variety of common CPU architectures—amd64, ppc32, sparcv9, and x86—are discussed in detail, along with several specific microarchitectures.
Original languageEnglish
Title of host publicationProgress in Cryptology - INDOCRYPT 2008 (Proceedings 9th International Conference on Cryptology in India, Kharagpur, India, December 14-17, 2008)
EditorsD.R. Chowdhury, V. Rijmen, A. Das
Place of PublicationBerlin
PublisherSpringer
Pages322-336
ISBN (Print)978-3-540-89753-8
DOIs
Publication statusPublished - 2008

Publication series

NameLecture Notes in Computer Science
Volume5365
ISSN (Print)0302-9743

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