This paper presents new speed records for AES software, taking advantage of (1) architecture-dependent reduction of instructions used to compute AES and (2) microarchitecture-dependent reduction of cycles used for those instructions. A wide variety of common CPU architectures—amd64, ppc32, sparcv9, and x86—are discussed in detail, along with several specific microarchitectures.
|Title of host publication||Progress in Cryptology - INDOCRYPT 2008 (Proceedings 9th International Conference on Cryptology in India, Kharagpur, India, December 14-17, 2008)|
|Editors||D.R. Chowdhury, V. Rijmen, A. Das|
|Place of Publication||Berlin|
|Publication status||Published - 2008|
|Name||Lecture Notes in Computer Science|