NeuroVP: A System-Level Virtual Platform for Integration of Neuromorphic Accelerators

Melvin Galicia, Ali Banagozar, Karl Sturm, Felix Staudigl, Sander Stuijk, Henk Corporaal, Rainer Leupers

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

7 Citations (Scopus)
1 Downloads (Pure)

Abstract

Executing neural network (NN) applications on general-purpose processors result in a large power and performance overhead, due to the high cost of data movement between the processor and the main memory. Neuromorphic computing systems based on memristor crossbars, perform the NN main operation i.e., vector-matrix multiplications (VMM) in an efficient way in the analog domain. Thus, they circumvent the costly energy overhead of its digital counterpart. It can be expected that neuromorphic systems will be used initially as complements to current high-performance systems rather than as a replacement. This paper presents NeuroVP, a virtual platform integrating a neuromorphic accelerator, developed in SystemC that can model functionality, timing, and power consumption of the components integrating the system. Using NeuroVP to evaluate performance and power consumption at the electronic system level (ESL), it is corroborated that the execution of NN applications with a neuromorphic accelerator yields of up to 46x higher power efficiency and 26x speedup relative to a general-purpose computing system.

Original languageEnglish
Title of host publicationProceedings 34th IEEE International System-on-Chip Conference (SOCC)
EditorsGang Qu, Jinjun Xiong, Danella Zhao, Venki Muthukumar, Md Farhadur Reza, Ramalingam Sridhar
PublisherInstitute of Electrical and Electronics Engineers
Pages236-241
Number of pages6
ISBN (Electronic)978-1-6654-2931-3
DOIs
Publication statusPublished - 24 Mar 2022
Event34th IEEE International System on Chip Conference, SOCC 2021 - Virtual, Online, Las Vegas, United States
Duration: 14 Sept 202117 Sept 2021
Conference number: 34

Conference

Conference34th IEEE International System on Chip Conference, SOCC 2021
Abbreviated titleSOCC
Country/TerritoryUnited States
CityLas Vegas
Period14/09/2117/09/21

Funding

This work was supported by the Federal Ministry of Education and Research (BMBF, Germany) within the NEUROTEC project (No. 16ES1134 and 16ES1133K).

Keywords

  • ESL Power Estimation
  • Memristor
  • Neuromorphic Accelerator
  • RISC-V
  • SystemC
  • Virtual Platform

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