Abstract
Nowadays, many real world problems need fast processing neural networks to come up with a solution in real time. Therefore hardware implementation becomes indispensable. The problem is then to choose the right chip that is to be used for a particular application. For this, a proper set of hardware performance criteria is needed to be able to compare the performance of neural network chips. The most important criterium is related to the speed a network processes information with a given accuracy. For this a new criterium is proposed. The 'effective number of connection bits' represents the effective accuracy of a chip. The '(effective) connection primitives per second' criterium now provides a new speed criterium normalized to the amount of information value that is processed in a connection. In addition to this the authors also propose another new criterium called 'reconfigurability number' as a measure for the reconfigurability and size of a chip. Using these criteria gives a much more neutral view of the performance of a neural network chip than the existing conventional criteria, such as 'connections per second'.
Original language | English |
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Title of host publication | The 1994 IEEE International Conference on Neural Networks : IEEE World Congress on Computational Intelligence, June 27-June 29, 1994, Orlando Florida |
Place of Publication | Piscataway |
Publisher | Institute of Electrical and Electronics Engineers |
Pages | 1885-1888 |
ISBN (Print) | 0-7803-1901-X |
DOIs | |
Publication status | Published - 1994 |
Event | IEEE International Conference on Neural Networks - Orlando, Fl., United States Duration: 27 Jun 1994 → 29 Jun 1994 |
Conference
Conference | IEEE International Conference on Neural Networks |
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Country/Territory | United States |
City | Orlando, Fl. |
Period | 27/06/94 → 29/06/94 |
Other | The 1994 IEEE International Conference on Neural Networks : IEEE World Congress on Computational Intelligence, June 27-June 29, 1994, Walt Disney World Dolphin Hotel, Orlando Florida. |